P2 Pin input voltage thresholds

Tubular

Did some testing today seeing how much the pin thresholds vary from pin to pin

This is for the ES2 glob top silicon

Here's a summary table

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Propeller 2 – comparison of pin voltage thresholds

Pin Threshold (V) VIO voltage Ratio Meas
0 1.64061 3.29674 0.4976221
1 1.65081 3.29674 0.500718
2 1.65416 3.29674 0.5017726
3 1.64695 3.29674 0.4996063
4 1.6536 3.29674 0.5015635
5 1.64503 3.29674 0.4990159
6 1.64999 3.29674 0.5005244
7 1.64823 3.29674 0.4999546
8 1.67355 3.321 0.5039354
9 1.67164 3.321 0.5033602
10 1.66274 3.321 0.5006757
11 1.67582 3.321 0.5046321
12 1.66639 3.321 0.5017685
13 1.67001 3.321 0.5028801
14 1.68074 3.321 0.5061023
15 1.67385 3.321 0.5040039
16 1.65266 3.3067 0.4997777
17 1.65493 3.3067 0.5004601
18 1.67238 3.3067 0.5057472
19 1.65237 3.3067 0.499694
20 1.65326 3.3067 0.4999712
21 1.65201 3.3067 0.4996064
22 1.65067 3.3067 0.4990103
note signal out on p23

mean 1.6588 3.30820956521739 0.501408804347826
stdev 0.011604785454912 0.0103947554426 0.002290411813404
min 1.64061 3.29674 0.4976221
max 1.68074 3.321 0.5061023

NOTES
Test board – P123-ES with 2nd Rev ES glob top chip (Sep 2019)
DMM – HP 34465A in 100 PLC, DCV, Ratio mode, second display shows both measurements
Each set of 8 pins has its own LDO, no jumpers for selection

cgracey

Thanks, Lachlan.

0.5014 is pretty close to ideal. That's just open loop, too, and is a function of the PMOS/NMOS ratio in the tiny input inverter. That ratio was determined via SPICE simulation. It's kind of amazing how closely the actual silicon correlates with the SPICE models.

Tubular

Yes I was impressed with how close to midpoint these were.