P.S. VonSzarvas has got the new P2 Eval board thoroughly tested for all kinds of operating and fault conditions. It is going to be a very solid platform for the new P2 silicon. Looks simple, too, without all the jumpers. We're ready to build those at Parallax as soon as we get Amkor-packages parts from ON Semi.
Any word about new accessory boards to be added to the currently available set?
P.S. VonSzarvas has got the new P2 Eval board thoroughly tested for all kinds of operating and fault conditions. It is going to be a very solid platform for the new P2 silicon. Looks simple, too, without all the jumpers. We're ready to build those at Parallax as soon as we get Amkor-packages parts from ON Semi.
Any word about new accessory boards to be added to the currently available set?
I know he's got a HyperRAM/HyperFlash board coming.
P.S. VonSzarvas has got the new P2 Eval board thoroughly tested for all kinds of operating and fault conditions. It is going to be a very solid platform for the new P2 silicon. Looks simple, too, without all the jumpers. We're ready to build those at Parallax as soon as we get Amkor-packages parts from ON Semi.
Any word about new accessory boards to be added to the currently available set?
I know he's got a HyperRAM/HyperFlash board coming.
Hooray!!!!
P.S. I know we'll be able to get many logic analyzers and DSOs coming. The best Chipmass ever!
I keep wracking my brain, trying to figure out if there's anything else I need to be worrying about, at this point. I'll probably transition back to working on Spin2 tomorrow.
Do you have a checklist of what you have covered so far ?
Did the new Analog modes and Analog filters get checked yet, with internal and external ADCs ?
I think the random number generator was tweaked, but that may have already been checked ?
I keep wracking my brain, trying to figure out if there's anything else I need to be worrying about, at this point. I'll probably transition back to working on Spin2 tomorrow.
Do you have a checklist of what you have covered so far ?
Did the new Analog modes and Analog filters get checked yet, with internal and external ADCs ?
I think the random number generator was tweaked, but that may have already been checked ?
All that has been verified, with the exception of an externally clocked sigma-delta modulator.
One thing comes to mind: this problem of the PLL getting jittery at elevated temperatures on the previous silicon. I will get a heat gun tomorrow and warm things up and see if I can get any pixel jitter at 1080p Y-Pb-Pr analog. It's such a shame that we cannot signal any higher resolutions than that on these nice big cheap TVs.
I really like the idea of 3840x2160 (4k), since it is great for showing lots of code. I suppose the 60fps pixel rate for that would be 4 x 148.5MHz, or 594MHz. At 24fps, though, that would drop to 237.6MHz, which would work great with Y-Pb-Pr, which takes only 3 pins.
I wish some big 4k TV manufacturer would start offering analog interfaces.
My 4k monitor doesn't have a VGA connector either. Even its DVI connector is DVI-D only. Maybe another one of those shall-not-go-past walls, like the minimum 30 KHz horizontal.
Yanomani pm'd me some special documents he found that contain timing data through 8k modes. I will try to get timing perfect in Y-Pb-Pr and see if I can get my 4k TV to receive and display a 4k picture tomorrow through the component video connectors.
Cluso,
Modern CPUs require really complex power delivery setups and significant active cooling. Yes they draw less power than previous generations, but it's still really high compared to most any microcontroller.
Also, going down to smaller processes means much more leakage and power draw until you get to the 22nm finfet and other smaller and more fancy setups which are stupidly expensive to make.
I am doubtful we could make a MCU in any of the processes smaller than 40nm without it being impractical due to power requirements and cooling requirements.
Sure, a P3 (or whatever) made at those sub 20nm process levels would be simpler than intel CPUs, but you still have to deal with the process requirements, and if you want it to run at 1 or 2Ghz, then you need to deal with the level of power needed for that.
I think the most practical process to try is something like 40-45nm, and run it at lower clock rates than it's capable of (like 1Ghz instead of 3Ghz). We could get a lot more ram and cores, but it will still require more considerations for power input, and likely require active cooling unless sufficiently under clocked.
Chip,
Really great hearing that everything is checking out, and we get better power and speed numbers. Can't wait to see this in the wild with everyone pushing it to do great things.
Cluso,
Modern CPUs require really complex power delivery setups and significant active cooling. Yes they draw less power than previous generations, but it's still really high compared to most any microcontroller.
Also, going down to smaller processes means much more leakage and power draw until you get to the 22nm finfet and other smaller and more fancy setups which are stupidly expensive to make.
I am doubtful we could make a MCU in any of the processes smaller than 40nm without it being impractical due to power requirements and cooling requirements.
Sure, a P3 (or whatever) made at those sub 20nm process levels would be simpler than intel CPUs, but you still have to deal with the process requirements, and if you want it to run at 1 or 2Ghz, then you need to deal with the level of power needed for that.
I think the most practical process to try is something like 40-45nm, and run it at lower clock rates than it's capable of (like 1Ghz instead of 3Ghz). We could get a lot more ram and cores, but it will still require more considerations for power input, and likely require active cooling unless sufficiently under clocked.
Chip,
Really great hearing that everything is checking out, and we get better power and speed numbers. Can't wait to see this in the wild with everyone pushing it to do great things.
Roy,
What i said (or meant if it wasn’t clear) was that the current P2 built at say 20nm (even without finfet) would indeed use way less power that it does at 180nm. Things have improved immensely. The hoohah is because these chips have billions of transistors. P2 has less than 1 million. The latest 8-10nm chips have 10+ billion IIRC. Thats like 10,000 P2’s.
If a 10 billion transistor chip at ~8nm uses ~80W, then by scaling a P2 with 1 million transistors would use ~80W / 10,000 = ~8mW. And 8mW at 0.9V core is ~7.2mA. No heatsink required here!
BTW I wasn’t suggesting even 20nm. I’m curious to know what 90nm would give?
A conservative P2 with 16 cores, 8KB Lut, and with1MB of hub (maybe 2MB hub in 8 x 256KB banks, selectable per cog) at 1GHz would be nice
BTW Congratulations on coming up with that egg-beater concept with Chip. I always thought it would be a power hog but it’s turned out nicely
I feel like I've sufficiently checked out the new silicon and it is good.
Speed is way higher and power consumption is much lower than I anticipated. We've got all the old silicon bugs fixed and all the new enhancements seem to work fine. Also, our I/O pins seem to synchronously interface all the way to the top end at 390MHz at room temperature, which was quite unexpected. Maybe tightening their propagation times to within 1ns of each other helped them work way beyond the timing spec of 175MHz at 150C junction temperature.
The only problem I can find is this P16 high-to-float 250mV downward glitch, which is pretty minor.
We need to get every die packaged that we can from these initial six engineering wafers. There should be at least 1,000 and maybe up to 2,400 chips from them. We are waiting to hear from ON Semi about when that can happen. We will build an initial run of 400 P2 Eval boards with more, as needed. The full mask set is ready to go, and was used to make these six engineering wafers.
As we transition from "engineering" to "production" at On Semi, there are some testing details to work out, but that all looks very promising.
I keep wracking my brain, trying to figure out if there's anything else I need to be worrying about, at this point. I'll probably transition back to working on Spin2 tomorrow.
P.S. VonSzarvas has got the new P2 Eval board thoroughly tested for all kinds of operating and fault conditions. It is going to be a very solid platform for the new P2 silicon. Looks simple, too, without all the jumpers. We're ready to build those at Parallax as soon as we get Amkor-packaged parts from ON Semi.
Sounds great! Congratulations on reaching the end of a very long road! I just got out my original P2-Eval board to start getting geared up to do some more P2 programming. It will be nice to have a near-production chip soon.
I keep wracking my brain, trying to figure out if there's anything else I need to be worrying about, at this point. I'll probably transition back to working on Spin2 tomorrow.
Was there a change to the PRNG implementation? I seem to recall that, but could be mistaken.
Was there a change to the PRNG implementation? I seem to recall that, but could be mistaken.
Yep, was tested on the FPGA. Changed the free running GETRND from the reference Xoroshiro128+ to the reference Xoroshiro128**. And updated the constants of our crafted Xoroshiro32++ in the XORO32 instruction.
If you remember P2-Hot from a few years ago, it was going to take 8W in a 180nm process. I had the engineer do a trial synthesis in a 40nm process, just for fun. It was going to take 89mW and run at 1.25GHz, if I recall. What we would build in such a small process is fractional in complexity to standard products.
Comments
P.S. Forget the complaining about a possible error on max-PLL.zip contents.
Perhaps I was momentarily catched inside a limbo, just when you was saving the last version to the post. It now downloads and unzips just right.
Any word about new accessory boards to be added to the currently available set?
I know he's got a HyperRAM/HyperFlash board coming.
Hooray!!!!
P.S. I know we'll be able to get many logic analyzers and DSOs coming. The best Chipmass ever!
+1, skip, +1, skip, +1 (A fat and old cannibal, jump-dancing over its left foot!
Yes, Ken and everyone at Parallax have kept the business running for these 13 years it took to make P2.
Did the new Analog modes and Analog filters get checked yet, with internal and external ADCs ?
I think the random number generator was tweaked, but that may have already been checked ?
All that has been verified, with the exception of an externally clocked sigma-delta modulator.
One thing comes to mind: this problem of the PLL getting jittery at elevated temperatures on the previous silicon. I will get a heat gun tomorrow and warm things up and see if I can get any pixel jitter at 1080p Y-Pb-Pr analog. It's such a shame that we cannot signal any higher resolutions than that on these nice big cheap TVs.
You should be able to support most any VGA mode tho ? My TV's here all have VGA connectors... (tho that is becoming less common with HDMI)
I found this table, for higher VGA pixel choices..
We've certainly got VGA covered.
I really like the idea of 3840x2160 (4k), since it is great for showing lots of code. I suppose the 60fps pixel rate for that would be 4 x 148.5MHz, or 594MHz. At 24fps, though, that would drop to 237.6MHz, which would work great with Y-Pb-Pr, which takes only 3 pins.
I wish some big 4k TV manufacturer would start offering analog interfaces.
Modern CPUs require really complex power delivery setups and significant active cooling. Yes they draw less power than previous generations, but it's still really high compared to most any microcontroller.
Also, going down to smaller processes means much more leakage and power draw until you get to the 22nm finfet and other smaller and more fancy setups which are stupidly expensive to make.
I am doubtful we could make a MCU in any of the processes smaller than 40nm without it being impractical due to power requirements and cooling requirements.
Look at this pinout for the 1151 socket for intel chips: https://techgage.com/wp-content/uploads/2017/10/Intel-Coffee-Lake-Pin-Diagram.jpg
Notice how many different power inputs and how many of the pins are just power and ground (like more than half). They have to feed in power all over the die.
Sure, a P3 (or whatever) made at those sub 20nm process levels would be simpler than intel CPUs, but you still have to deal with the process requirements, and if you want it to run at 1 or 2Ghz, then you need to deal with the level of power needed for that.
I think the most practical process to try is something like 40-45nm, and run it at lower clock rates than it's capable of (like 1Ghz instead of 3Ghz). We could get a lot more ram and cores, but it will still require more considerations for power input, and likely require active cooling unless sufficiently under clocked.
Chip,
Really great hearing that everything is checking out, and we get better power and speed numbers. Can't wait to see this in the wild with everyone pushing it to do great things.
Nice work everyone. I gotta shake time loose. Best way to do that is get these specd into a product.
Gonna start that advocacy right away.
@Chip, how in the world did he find those? Any chance we can see em?
Maybe, just maybe an adapter can be made. One pin super high res monochrome, is as compelling to me as 3 pin color is.
Someone made something that will do it. Wonder what it is?
Roy,
What i said (or meant if it wasn’t clear) was that the current P2 built at say 20nm (even without finfet) would indeed use way less power that it does at 180nm. Things have improved immensely. The hoohah is because these chips have billions of transistors. P2 has less than 1 million. The latest 8-10nm chips have 10+ billion IIRC. Thats like 10,000 P2’s.
If a 10 billion transistor chip at ~8nm uses ~80W, then by scaling a P2 with 1 million transistors would use ~80W / 10,000 = ~8mW. And 8mW at 0.9V core is ~7.2mA. No heatsink required here!
BTW I wasn’t suggesting even 20nm. I’m curious to know what 90nm would give?
A conservative P2 with 16 cores, 8KB Lut, and with1MB of hub (maybe 2MB hub in 8 x 256KB banks, selectable per cog) at 1GHz would be nice
BTW Congratulations on coming up with that egg-beater concept with Chip. I always thought it would be a power hog but it’s turned out nicely
Renewed enthusiasm too!
Was there a change to the PRNG implementation? I seem to recall that, but could be mistaken.
Yanomani, do you have links to those papers?
They were from some standards organizations that usually want money for access to their standards.