Chip: Did you ever hear from On Semi about when they can deliver chips in the production packages?
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
All my time has been going to resolve this problem.
Wow! Sorry for distracting you from this. Good luck in resolving this problem.
Chip: Did you ever hear from On Semi about when they can deliver chips in the production packages?
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
All my time has been going to resolve this problem.
Wow! Sorry for distracting you from this. Good luck in resolving this problem.
Distraction is welcome. Anything to reseed the random number generator.
Chip: Did you ever hear from On Semi about when they can deliver chips in the production packages?
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
All my time has been going to resolve this problem.
Hi Chip,
Is there any chance that some inductive spikes are causing pins to latch up? The long wires on their setup may cause this. Even the internal ESD protection may not be enough to stop this. Just an hypothesis. I've seen this behaviour before on other chips, namely fast op-amps.
Chip: Did you ever hear from On Semi about when they can deliver chips in the production packages?
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
All my time has been going to resolve this problem.
Hi Chip,
Is there any chance that some inductive spikes are causing pins to latch up? The long wires on their setup may cause this. Even the internal ESD protection may not be enough to stop this. Just an hypothesis. I've seen this behaviour before on other chips, namely fast op-amps.
Kind regards, Samuel Lourenço
Not sure. I've had several theories, but none have panned out, so far.
They are seeing huge VIO currents of up to 500mA when there is no pin loading. Seems like latch-up to me.
I will be doing some experiments today to simulate what I think may be happening.
Maybe they placed the chips upside down? Or by accident they discovered something like a Positron, that actually is a negative Elektron, or a wormhole where something flows out that flows in from another world where borders don't exist?
Maybe they placed the chips upside down? Or by accident they discovered something like a Positron, that actually is a negative Elektron, or a wormhole where something flows out that flows in from another world where borders don't exist?
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
..
They are seeing huge VIO currents of up to 500mA when there is no pin loading. Seems like latch-up to me.
Does that cause permanent damage ? What are the IO and pin voltages when this occurs ?
By random, is that the same pin every time, on a given die, but varies with a new die, or does the pin wander per test ?
Do you mean you placed a part that they 'failed' on their tester, but it all works OK on Eval ?
Their package part testing is quite different FWIR, it has a ZIF socket, and some decoupling ?
How do they connect to the PAD in the ZIF ? I think P2 is a little unusual, in that there are no ground pins, just the PAD.
I was also thinking about the ground connection being missing or intermittent at the wrong moment.
I wonder if at least one of the GND pad pogos could be verified for continuity before applying VDD and VIO.
Either add a "fake" GND pogo, or re-purpose one.
Can they provide you with a V-I profile (or I vs time) as the pins are being brought up, Chip?
One unusual thing about the P2ES board is the size of the caps on each of the VIO pins, I think there are twin 4.7uF caps on each of the 8 VIO buses, so they are likely being brought up relatively slowly.
Here is a plot of total VIO current during the test suite.
Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.
I'm asking them to let me come there Thursday morning. I think we could get to the bottom of the problem in just an hour, or two.
Something really silly is going on.
By the way, as soon as we resolve this problem, it will be seven weeks, fastest route, to get packaged chips from Amkor.
Can they provide you with a V-I profile (or I vs time) as the pins are being brought up, Chip?
One unusual thing about the P2ES board is the size of the caps on each of the VIO pins, I think there are twin 4.7uF caps on each of the 8 VIO buses, so they are likely being brought up relatively slowly.
We're being held up by testing troubles.
On their test setup, they are getting huge currents on random VIO pins, on both dies and packaged parts. When we put a packaged chip on an Eval board, though, there are no high currents. It's not making any sense.
..
They are seeing huge VIO currents of up to 500mA when there is no pin loading. Seems like latch-up to me.
Does that cause permanent damage ? What are the IO and pin voltages when this occurs ?
By random, is that the same pin every time, on a given die, but varies with a new die, or does the pin wander per test ?
Do you mean you placed a part that they 'failed' on their tester, but it all works OK on Eval ?
Their package part testing is quite different FWIR, it has a ZIF socket, and some decoupling ?
How do they connect to the PAD in the ZIF ? I think P2 is a little unusual, in that there are no ground pins, just the PAD.
I believe it can cause permanent damage. Check out this probe-pin mishap on VIO_44_47. I can't image this didn't also fry some electronics on the die.
This happens on various VIO pins. Voltage is ~3.3V.
They sent us parts that passed all their tests, but they were having these high-current issues, all along, during testing.
They have some pogo pins that connect the socket board to the bottom pad of the chip.
I second going there physically and putting eyes on, Chip. In thirty-five years of troubleshooting stuff I've never learned to see through a telephone, and many times I've resolved an issue in five minutes once I could see the layout with my own eyes.
Here is a plot of total VIO current during the test suite.
Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.
Certainly strange.
Too low to be a latch-up SCR effect, and rather high for a stuck-pin.
What are the pin voltages during that test ?
Are they all floating, or pulled to a GND level ?
Is there a RESET pulse generated before they start any tests ?
Did anything similar happen on the ES1 die testing ?
minus 22mA is also strange. Is that coming from the 1v8 via some feed thru mechanism ? No sign of that on ES1, seems fine with VCore and no VIO, VIO is low mV.
Did you check what the latch up current is for P2 ?
Usually it is > 100mA, and if this was latchup, I'd expect 3v3 to sag severely, and probably no pass to tests.
This seems to be passing the tests, but with the unexplained (and somewhat variable) offset current ?
I believe it can cause permanent damage. Check out this probe-pin mishap on VIO_44_47. I can't image this didn't also fry some electronics on the die.
This happens on various VIO pins. Voltage is ~3.3V.
Have they lowered some current trip to try to preserve probes ?
the VIO base current changes each time he re-seats the test head.
There has to be a clue there. If the worst is 500mA, what is the best number they have seen ?
Is it possible a probe(s) is damaged enough, to also contact other near-PAD metal, as well as the PAD ?
Here is a plot of total VIO current during the test suite.
Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.
Certainly strange.
Too low to be a latch-up SCR effect, and rather high for a stuck-pin.
What are the pin voltages during that test ?
Are they all floating, or pulled to a GND level ?
Is there a RESET pulse generated before they start any tests ?
Did anything similar happen on the ES1 die testing ?
minus 22mA is also strange. Is that coming from the 1v8 via some feed thru mechanism ? No sign of that on ES1, seems fine with VCore and no VIO, VIO is low mV.
Did you check what the latch up current is for P2 ?
Usually it is > 100mA, and if this was latchup, I'd expect 3v3 to sag severely, and probably no pass to tests.
This seems to be passing the tests, but with the unexplained (and somewhat variable) offset current ?
I believe it can cause permanent damage. Check out this probe-pin mishap on VIO_44_47. I can't image this didn't also fry some electronics on the die.
This happens on various VIO pins. Voltage is ~3.3V.
Have they lowered some current trip to try to preserve probes ?
the VIO base current changes each time he re-seats the test head.
There has to be a clue there. If the worst is 500mA, what is the best number they have seen ?
Is it possible a probe(s) is damaged enough, to also contact other near-PAD metal, as well as the PAD ?
The pins are pulled down with 500ua on the digital tests and floating on the I/O test. Only a few pins output on the digital tests.
The engineer was going to check if the prior die and test patterns caused these same current flows on VIO. These flows have ranged from 120mA to 500mA.
The chips can pass the test when packaged, but these crazy currents can blow wafer prober pins. When placed on the P2 Eval board, these currents don't exist.
They are certainly going to set current limits when they use the probe card next time. Right now, they are just working with packaged parts, since it's safer.
I second going there physically and putting eyes on, Chip. In thirty-five years of troubleshooting stuff I've never learned to see through a telephone, and many times I've resolved an issue in five minutes once I could see the layout with my own eyes.
The chips can pass the test when packaged, but these crazy currents can blow wafer prober pins. When placed on the P2 Eval board, these currents don't exist.
How closely have you looked at the P2 Eval board though? It may be working but there may be clues to whats going on contained therein.
Are you now using the v2 of the P2ES board (which I think does away with the individual VIO jumpers?) Just wondering whether its worth looking back at the P2ES v1 board which had the jumpers, for similar signs. This one area we could help you out with...
Completely agree with the 'going there' to help resolve it
The other question is, what current flows (if any) occur during reset? And what does the VIO profile look like coming out of reset to get to that -22mA baseline? (are there time delays getting there, is it a single RC time constant rise etc)
Here is a plot of total VIO current during the test suite.
Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.
I'm asking them to let me come there Thursday morning. I think we could get to the bottom of the problem in just an hour, or two.
Something really silly is going on.
By the way, as soon as we resolve this problem, it will be seven weeks, fastest route, to get packaged chips from Amkor.
Image clearly shows voltage and current profiles, along 60000 samples, but there ain't a word about used sample rate, thus we can't estimate the clock frequencies involved.
Is it possible for the ATE to be programmed to do a SCAN-only pass first, then power off DUT, then restart the test, but without the SCAN pass?
The second part would closelly mimics the setup you have, with the globe top seating onto the EVAL board, so a better compare with results you've got could be extracted.
P.S. if the above is feasible, perhaps ensureing total VIO and VDD bleeding, prior to second test instance, could result meaningfull data.
..
Note that there's a base current of ~125mA that shouldn't be there.
Perhaps focus on 'What can draw 125mA ?'
eg Suppose some pins powered up, without a reset, and the higher current DACs enabled ?
Could that draw 125mA/group and then up to 4 x 125mA = 500mA, if 4 groups init that bad way.
Does the reset pin, work during their SCAN phase ?
Looking at the datasheet there are 16 each Vio, Gio, Vdd, Vss. The Vio feed their designated IO pins. Are the Gio tied together on chip?
What about the Vdd? Are those tied together on die or do they feed separate areas of the chip?
What would happen if a single power pin got mixed up? I've seen 1.8v DDR2 rams run on 3.3v for a fairly long time. Although at higher current. It would be great to get a thermal camera on the die to see where the power is going.
Given the design of the P2, is high Vio current a likely result of a fabrication defect? It sounds like no parts that have failed the probe test or packaged test were mounted on eval boards.
Are the chips tested in the dark? For how long? Could the -22mA be photovoltaic action?
Comments
Distraction is welcome. Anything to reseed the random number generator.
Is there any chance that some inductive spikes are causing pins to latch up? The long wires on their setup may cause this. Even the internal ESD protection may not be enough to stop this. Just an hypothesis. I've seen this behaviour before on other chips, namely fast op-amps.
Kind regards, Samuel Lourenço
Not sure. I've had several theories, but none have panned out, so far.
They are seeing huge VIO currents of up to 500mA when there is no pin loading. Seems like latch-up to me.
I will be doing some experiments today to simulate what I think may be happening.
We need to get this straightened out ASAP.
We've already ruled those out.
By random, is that the same pin every time, on a given die, but varies with a new die, or does the pin wander per test ?
Do you mean you placed a part that they 'failed' on their tester, but it all works OK on Eval ?
Their package part testing is quite different FWIR, it has a ZIF socket, and some decoupling ?
How do they connect to the PAD in the ZIF ? I think P2 is a little unusual, in that there are no ground pins, just the PAD.
I wonder if at least one of the GND pad pogos could be verified for continuity before applying VDD and VIO.
Either add a "fake" GND pogo, or re-purpose one.
One unusual thing about the P2ES board is the size of the caps on each of the VIO pins, I think there are twin 4.7uF caps on each of the 8 VIO buses, so they are likely being brought up relatively slowly.
Note that there's a base current of ~125mA that shouldn't be there. Also, the test starts off at -22mA, which is weird.
Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.
I'm asking them to let me come there Thursday morning. I think we could get to the bottom of the problem in just an hour, or two.
Something really silly is going on.
By the way, as soon as we resolve this problem, it will be seven weeks, fastest route, to get packaged chips from Amkor.
That shouldn't matter. You can pull the VDD and VIO jumpers on your P2 Eval and verify.
I believe it can cause permanent damage. Check out this probe-pin mishap on VIO_44_47. I can't image this didn't also fry some electronics on the die.
This happens on various VIO pins. Voltage is ~3.3V.
They sent us parts that passed all their tests, but they were having these high-current issues, all along, during testing.
They have some pogo pins that connect the socket board to the bottom pad of the chip.
Presumably the 1v8 core is powered at that stage (the -22mA stage), right?
I believe VDD is powered up simultaneously with VIO. They've tried every variation and it doesn't make a difference.
Yes, that -22mA could be from GND being maybe 400mV, or from I/O's being pulled high while VIO is at GND.
I don't know if the -22mA is consistent.
Certainly strange.
Too low to be a latch-up SCR effect, and rather high for a stuck-pin.
What are the pin voltages during that test ?
Are they all floating, or pulled to a GND level ?
Is there a RESET pulse generated before they start any tests ?
Did anything similar happen on the ES1 die testing ?
minus 22mA is also strange. Is that coming from the 1v8 via some feed thru mechanism ? No sign of that on ES1, seems fine with VCore and no VIO, VIO is low mV.
Did you check what the latch up current is for P2 ?
Usually it is > 100mA, and if this was latchup, I'd expect 3v3 to sag severely, and probably no pass to tests.
This seems to be passing the tests, but with the unexplained (and somewhat variable) offset current ?
Have they lowered some current trip to try to preserve probes ?
There has to be a clue there. If the worst is 500mA, what is the best number they have seen ?
Is it possible a probe(s) is damaged enough, to also contact other near-PAD metal, as well as the PAD ?
The pins are pulled down with 500ua on the digital tests and floating on the I/O test. Only a few pins output on the digital tests.
The engineer was going to check if the prior die and test patterns caused these same current flows on VIO. These flows have ranged from 120mA to 500mA.
The chips can pass the test when packaged, but these crazy currents can blow wafer prober pins. When placed on the P2 Eval board, these currents don't exist.
They are certainly going to set current limits when they use the probe card next time. Right now, they are just working with packaged parts, since it's safer.
That's what I'm thinking.
How many parts have you mounted and checked ? Might pay to check all the glob packages you have, to confirm with a larger sample size ?
How closely have you looked at the P2 Eval board though? It may be working but there may be clues to whats going on contained therein.
Are you now using the v2 of the P2ES board (which I think does away with the individual VIO jumpers?) Just wondering whether its worth looking back at the P2ES v1 board which had the jumpers, for similar signs. This one area we could help you out with...
Completely agree with the 'going there' to help resolve it
Image clearly shows voltage and current profiles, along 60000 samples, but there ain't a word about used sample rate, thus we can't estimate the clock frequencies involved.
Is it possible for the ATE to be programmed to do a SCAN-only pass first, then power off DUT, then restart the test, but without the SCAN pass?
The second part would closelly mimics the setup you have, with the globe top seating onto the EVAL board, so a better compare with results you've got could be extracted.
P.S. if the above is feasible, perhaps ensureing total VIO and VDD bleeding, prior to second test instance, could result meaningfull data.
Do they break this current down further, into per IO groups ?
The inference here is just one IO group is the offender ?
Perhaps focus on 'What can draw 125mA ?'
eg Suppose some pins powered up, without a reset, and the higher current DACs enabled ?
Could that draw 125mA/group and then up to 4 x 125mA = 500mA, if 4 groups init that bad way.
Does the reset pin, work during their SCAN phase ?
What about the Vdd? Are those tied together on die or do they feed separate areas of the chip?
What would happen if a single power pin got mixed up? I've seen 1.8v DDR2 rams run on 3.3v for a fairly long time. Although at higher current. It would be great to get a thermal camera on the die to see where the power is going.
Given the design of the P2, is high Vio current a likely result of a fabrication defect? It sounds like no parts that have failed the probe test or packaged test were mounted on eval boards.
Are the chips tested in the dark? For how long? Could the -22mA be photovoltaic action?
Each of the 16 VIO pads are unique and go to a pin.
Each of the 16 GIO pads are unique and go to GND.