riscvp2: a C and C++ compiler for P2

Rayman

@ersmith I'll try that thanks.

On another front, I'm having problem with loadp2 and the -HIMEM=flash .elf outputs.
Seems above some size, it gives me:

ERROR: timeout waiting for checksum at end: got 1     
Try increasing the FIFO setting if not large enough for your setup              
Press enter to continue...   

On one computer, was able to fix it by adding the "-v" verbose option.
Haven't found a solution yet on another...

WAIT A SEC. Seems the binary on the working PC also works on this problem PC...
Must be a problem in the code somewhere...

Rayman

@ersmith Ok, does seem there is a problem with loadp2 and -himem=flash.
One setup did not have "#define MICROPY_PY_SELECT (1)" in it and was just a hair smaller and that works.
But, when that is added, it can no longer load.
The difference in code size is tiny:

text data bss dec
294540 16936 217640 529116 --> Won't load
292848 16904 217640 527392 --> Loads ok

Here are two elf examples. Smaller one loads, bigger one won't...

Rayman

Added an extra delay in loadp2.c and seems to have fixed it:

static int verify_chksum(unsigned chksum)
{
    unsigned recv_chksum = 0;
    int num;
    wait_drain();
    //msleep(1+fifo_size*10*1000/loader_baud);
    //num = rx_timeout((uint8_t *)buffer, 3, 400);
    msleep(50);//RJA

Rayman

@ersmith Watching this video about RISCV in FPGA...
They are making a big deal about being able to create custom instructions.
But, this is something that already exists in riscvp2, right?

Know there are custom instructions available, but not sure if they are considered part of ALU or not...

ersmith

@Rayman said:
@ersmith Watching this video about RISCV in FPGA...
They are making a big deal about being able to create custom instructions.
But, this is something that already exists in riscvp2, right?

Know there are custom instructions available, but not sure if they are considered part of ALU or not...

Yes, riscvp2 has custom instructions for a bunch of P2 operations (such as pin manipulation). It uses the standard instruction space that RISC-V reserves for custom instructions.

riscvp2 isn't an interpreter, so "considered part of the ALU" doesn't really apply.

Rayman

Trying tensorflow lite micro again...

The issue before was that it downloads its own copy of riscv build tools.
So, I just replaced that with the riscvp2 build tools.

@ersmith To get rid of some errors/warnings had to change/add "-std=c++17" in CXXFLAGS.
Does this sound like a good thing to do?

ersmith

@Rayman said:
@ersmith To get rid of some errors/warnings had to change/add "-std=c++17" in CXXFLAGS.
Does this sound like a good thing to do?

That sounds reasonable to me; some newer gcc features may cause old code to give warnings, and using -std=c++17 will disable those features.