How are the values of _XDIV, _XMUL and _XDIVP determined? Does _CLOCKFREQ/_XMUL have to be within a certain range?
_XTALFREQ /_XDIV sets the Phase Frequency Detector frequency, and that shows to be 'higher is better' as a general rule.
Certainly _XDIV legal values of 64 or 40 are going to give larger jitter, probably not good enough for video applications.
Smallest _XDIV of value like 2, reduce the jitter to below the monitor sampling eye, where it becomes invisible to the human eye.
EDIT: So I see in the P2 documentation that the VCO frequency should be between 100 MHz and 400 MHz. However, the document also says between 100 MHz and 200 MHz. The VCO frequency is _XTALFREQ/_XDIV*_XMUL, so in the code above the VCO frequency is 250 MHz.
The original VCO target was 100~200MHz to cover 180MHz, but the stretch result has come in over 300MHz (varies with PVT).
IIRC Chip was wanting to nudge the upper VCO limit a little, so it better matches the counter limit.
Ideally, you do not want the counter to fail, at any real VCO value, but you also do not want too much dead-space either.
In the lower resolutions VGA, (25~31MHz) the exactly 250MHz nominal clock may be less than ideal, it may be better to target a clean multiple of the pixel clock, and to maybe also do some fine control on the Sync-timing, to improve the monitor sampling eye.
Might some of this jitter be marginalzed by dropping xzero consistently, each frame, say in the vblank?
Wait! Probably not. This is sysclock.
But I'm leaving it, in case I'm wrong. Personally, I've only had time for serial comms on my P2 so far. That's gonna change, and I can't wait, but it's not gonna change this week.
jmg, thanks for the information. I was having a problem with loadp2 only working up to 200 MHz. I was computing the clock mode for the higher frequencies. I modified it to use the formulas from the VGA examples for frequencies above 180 MHz. It works fine now.
Comments
http://pinouts.ru/Video/VGA15_pinout.shtml
_XTALFREQ /_XDIV sets the Phase Frequency Detector frequency, and that shows to be 'higher is better' as a general rule.
Certainly _XDIV legal values of 64 or 40 are going to give larger jitter, probably not good enough for video applications.
Smallest _XDIV of value like 2, reduce the jitter to below the monitor sampling eye, where it becomes invisible to the human eye.
The original VCO target was 100~200MHz to cover 180MHz, but the stretch result has come in over 300MHz (varies with PVT).
IIRC Chip was wanting to nudge the upper VCO limit a little, so it better matches the counter limit.
Ideally, you do not want the counter to fail, at any real VCO value, but you also do not want too much dead-space either.
In the lower resolutions VGA, (25~31MHz) the exactly 250MHz nominal clock may be less than ideal, it may be better to target a clean multiple of the pixel clock, and to maybe also do some fine control on the Sync-timing, to improve the monitor sampling eye.
Wait! Probably not. This is sysclock.
But I'm leaving it, in case I'm wrong. Personally, I've only had time for serial comms on my P2 so far. That's gonna change, and I can't wait, but it's not gonna change this week.
Is it possible to have HSync on a separate pin, just like VSync, and free the extra DAC on P0 for other purposes?
For example, a configuration like this:
P0 <extra dac>
P1 Blue DAC
P2 Green DAC
P3 Red DAC
P4 VSync
P5 HSync
And with "other purposes" I mean something that's still synchronous to the VGA signal, like an overlay.