I see there are 148.5000MHz oscillators at Digikey. I presume for this purpose.
Can you connect one of these to XI?
Worth trying too. Depends on if the Xtal amplifier can pass 148.5MHz, but a CMOS drive Osc might have enough.
You would need XI/XO loading caps = OFF
I see Mouser & MicrochipDirect have DSC1001CE5-148.5000, which is ±10ppm, 1.8~3.3 V 3.2 mm x 2.5 mm
Digikey have DSC1001AE2-148.5000, ±25ppm -20°C ~ 70°C 10.5mA (7.00mm x 5.00mm)
There are also plenty at 74.25MHz.
An appeal of 148.5Mhz testing, is you can bypass VCO entirely, and then enable, with a wide choice of PFD.
eg 148.5 74.25 49.5 37.125 29.7 24.75 21.214285 18.5625 16.5MHz
I guess it's ok with a PFD of 148.5MHz ?
Addit: Some of the 74.25MHz candidates : (no VCO bypass choice, but lower Icc, and still high PLL)
IT1602BC-12-33E-74.250000D SiTIME MEMS 74.2500MHZ $0.69888/1k HCMOS 3.3V ±25ppm -20~70°C 4.5mA (2.50mm x 2.00mm)
Peak-to-peak Period Jitter Typ 12ps Max 25ps (75MHz)
DSC1033CE2-074.2500 Microchip MEMS 74.2500MHZ $1.09180/1k CMOS 3.3V ±25ppm -20~70°C 4mA (Typ) (3.20mm x 2.50mm)
Jitter, Cycle to Cycle JCC F = 100MHz Typical 95 ps
Makes the SiTime one look better than Microchip, for jitter testing ?
FWIW When I was doing the first testing with the osc divided to 0.5MHz and them multiplying up, when it lost sync I touched the P2 chip and the cooling brought it back into sync again.
BTW the code I posted changed the porch settings (see the +32 and -32 in the constants) to save having to adjust the xy settings in the monitor between this and VGA from my laptop.
Sorry I haven't had time to try with the P2_EVAL pcb yet.
It's still stable after running overnight with XDIV=15 and XMUL=111.
But, I just remembered a lot of talk about using a good power supply.
I'm just plugged into a USB port on a monitor...
Never mind, tried powering from unplugged laptop and got same result.
It's still stable after running overnight with XDIV=15 and XMUL=111.
With the new porch settings, I'm curious about what works and what does not. ie it's not clear if 15,111 is ok and 10,74 is not, as both give 148MHz ?
Perhaps that means there are 'good' and 'bad' PFD areas, rather than the expected faster is better ?
It does seem that ppm = -3378 is sync-tolerated, (do 1920 pixels still display?) so maybe +480ppm is also ok ? (or is tolerance skewed more -ppm ?)
If 1920 pixels do not fit at 148MHz, a similar PFD setting is XDIV=13; XMUL=193; XDIVP = 2 for PFD = 1.538M & ppm = -259.0673
One pixel at 1920 scan, is 520ppm.
Table of test candidates 20MHz Xtal, 148.5MHz target SysCLK
I think I know what the problem is. There is a second order RC filter on the charge pump for the VCO. The first R is proportional to the divisor. The second R is fixed. It needs to be proportional, too, in order to avoid ringing. That flicker is the VCO wandering above and below the reference frequency because the second R is not dampening enough.
I reviewed the schematic and there is, in fact, a proportional resistor for the 2nd R. I need to do some simulations to find if, perhaps, the relative R's become skewed over different settings, since the first proportional resistor is used to set charge pump current and the second R is used a straight resistor.
I think I know what the problem is. There is a second order RC filter on the charge pump for the VCO. The first R is proportional to the divisor. The second R is fixed. It needs to be proportional, too, in order to avoid ringing. That flicker is the VCO wandering above and below the reference frequency because the second R is not dampening enough.
I reviewed the schematic and there is, in fact, a proportional resistor for the 2nd R. I need to do some simulations to find if, perhaps, the relative R's become skewed over different settings, since the first proportional resistor is used to set charge pump current and the second R is used a straight resistor.
I'm not sure that's the problem area, as that will affect during lock-characteristics more than locked (unless there is severe ringing, and the loop is marginally unstable)
Once nominally locked, there is very little dynamic action on the control voltage.
It seems 0.5MHz PFD is too low, but less clear if things improve as PFD rises, or if there are good and bad PFD values ?
Temperature will change the R's but not by huge amounts.
Temperature will be moving the VCO operating point slowly up, as the gates slow down needing a little more Vcc for the same MHz, That will change the loop-gain.
A spectrum plot of the VCO noise could help - ie is it random (likely dead-band issues), or some frequency peaks (loop stability?)
I think I know what the problem is. There is a second order RC filter on the charge pump for the VCO. The first R is proportional to the divisor. The second R is fixed. It needs to be proportional, too, in order to avoid ringing. That flicker is the VCO wandering above and below the reference frequency because the second R is not dampening enough.
I reviewed the schematic and there is, in fact, a proportional resistor for the 2nd R.
How proportional is that ? - is there a binary selection, meaning /8 thru /15 will have the same R, then /16 thru /31 have another R value etc.
Connecting a IT1602BC-12-33E-74.250000D oscillator would allow a PFD right up to 74.25MHz, and all proportional taps can be checked ?
I think I know what the problem is. There is a second order RC filter on the charge pump for the VCO. The first R is proportional to the divisor. The second R is fixed. It needs to be proportional, too, in order to avoid ringing. That flicker is the VCO wandering above and below the reference frequency because the second R is not dampening enough.
I reviewed the schematic and there is, in fact, a proportional resistor for the 2nd R. I need to do some simulations to find if, perhaps, the relative R's become skewed over different settings, since the first proportional resistor is used to set charge pump current and the second R is used a straight resistor.
I'm not sure that's the problem area, as that will affect during lock-characteristics more than locked (unless there is severe ringing, and the loop is marginally unstable)
Once nominally locked, there is very little dynamic action on the control voltage.
It seems 0.5MHz PFD is too low, but less clear if things improve as PFD rises, or if there are good and bad PFD values ?
Temperature will change the R's but not by huge amounts.
Temperature will be moving the VCO operating point slowly up, as the gates slow down needing a little more Vcc for the same MHz, That will change the loop-gain.
A spectrum plot of the VCO noise could help - ie is it random (likely dead-band issues), or some frequency peaks (loop stability?)
Yes, but I do not have easy access to a 1920x1080 display, or a spectrum analyser.... I do have a good counter, and a 100Msps scope.
If you use your scope and look at the signal maybe 1ms after triggering on a rise, you will see what kind of long-term jitter exists at different settings.
I was just looking at hsync and vsync with a scope and don't see an obvious difference between the two settings(15;111 vs. 40;297) ...
Yes, it will be a challenge to get enough zoom. eg 10ns scope capture is only going to resolve just over 1000 steps in horizontal axis.
A 1ns scope might be good enough ?
Is the jitter even over the screen, or favouring the right side, or more area based - you mentioned a pie-shape ? Can you post a photo, with area mark-ups ?
Thanks, if we suppose the PLL R's are binary switched, that suggests >= 32 is a problem. - a combination of less frequent PFD updates, and change in R ?
Other test points could be
and a close to correct value, bumped >= 32 is
148.5/(20/33) = 245.025 => try 33 & 245
That last one is in the same band as /40, so should be poor too ?
XDIV=1, XMUL=7 also looks good. Monitor says 57 Hz. Looks good on scope too.
So, XDIV decides the PLL frequency, right? What is the allowable range?
I think XMUL multiplies this to give VCO frequency that should be between 100 and 300 MHz.
BTW: I don't see the utility of the XDIVP when VCO is limited to 100 to 300 MHz... Am I missing something? Maybe for low power standby?
XDIV=2, XMUL=15 also looks good. Monitor says 61 Hz.
XDIV=3, XMUL=20 also looks OK, like the above. Monitor says 54 Hz. But, I think I do actually see some imperfections in the display when it is close to all white. Not horrible though.
Comments
Worth trying too. Depends on if the Xtal amplifier can pass 148.5MHz, but a CMOS drive Osc might have enough.
You would need XI/XO loading caps = OFF
I see Mouser & MicrochipDirect have DSC1001CE5-148.5000, which is ±10ppm, 1.8~3.3 V 3.2 mm x 2.5 mm
Digikey have DSC1001AE2-148.5000, ±25ppm -20°C ~ 70°C 10.5mA (7.00mm x 5.00mm)
There are also plenty at 74.25MHz.
An appeal of 148.5Mhz testing, is you can bypass VCO entirely, and then enable, with a wide choice of PFD.
eg 148.5 74.25 49.5 37.125 29.7 24.75 21.214285 18.5625 16.5MHz
I guess it's ok with a PFD of 148.5MHz ?
Addit: Some of the 74.25MHz candidates : (no VCO bypass choice, but lower Icc, and still high PLL)
IT1602BC-12-33E-74.250000D SiTIME MEMS 74.2500MHZ $0.69888/1k HCMOS 3.3V ±25ppm -20~70°C 4.5mA (2.50mm x 2.00mm)
Peak-to-peak Period Jitter Typ 12ps Max 25ps (75MHz)
DSC1033CE2-074.2500 Microchip MEMS 74.2500MHZ $1.09180/1k CMOS 3.3V ±25ppm -20~70°C 4mA (Typ) (3.20mm x 2.50mm)
Jitter, Cycle to Cycle JCC F = 100MHz Typical 95 ps
Makes the SiTime one look better than Microchip, for jitter testing ?
What happened? Investigating...
Watched it this time (after power cycle)... It was perfectly fine for ~5 minutes and then started flickering.
Did it have time to cool down ? Is the flickering bad enough to see on a scope ?
Instead, I'm trying XDIV=15, XMUL=111. Looks good after 5 minutes...
Is that better than /7 & * 52 ?
Seems surprising, as
XDIV=15;XMUL=111; ppm = -3378
vs
XDIV=7;XMUL=52; ppm = 480
Was the earlier test XDIV=10 and XMUL=74 ?
Strange, as that also gives exactly the same ppm as 15,111
XDIV=10;XMUL=74; ppm = -3378
Monitor says 1080p @ 60 Hz
Working pretty good here, considering some fairly long leads between P2 and VGA connector.
Is that showing all 1920 pixels ok, as that's 148MHz, some distance from 148.5MHz ?
But, still stable after ~1 hour, so that's good...
BTW the code I posted changed the porch settings (see the +32 and -32 in the constants) to save having to adjust the xy settings in the monitor between this and VGA from my laptop.
Sorry I haven't had time to try with the P2_EVAL pcb yet.
But, I just remembered a lot of talk about using a good power supply.
I'm just plugged into a USB port on a monitor...
Never mind, tried powering from unplugged laptop and got same result.
With the new porch settings, I'm curious about what works and what does not. ie it's not clear if 15,111 is ok and 10,74 is not, as both give 148MHz ?
Perhaps that means there are 'good' and 'bad' PFD areas, rather than the expected faster is better ?
It does seem that ppm = -3378 is sync-tolerated, (do 1920 pixels still display?) so maybe +480ppm is also ok ? (or is tolerance skewed more -ppm ?)
If 1920 pixels do not fit at 148MHz, a similar PFD setting is XDIV=13; XMUL=193; XDIVP = 2 for PFD = 1.538M & ppm = -259.0673
One pixel at 1920 scan, is 520ppm.
Table of test candidates 20MHz Xtal, 148.5MHz target SysCLK
I reviewed the schematic and there is, in fact, a proportional resistor for the 2nd R. I need to do some simulations to find if, perhaps, the relative R's become skewed over different settings, since the first proportional resistor is used to set charge pump current and the second R is used a straight resistor.
I'm not sure that's the problem area, as that will affect during lock-characteristics more than locked (unless there is severe ringing, and the loop is marginally unstable)
Once nominally locked, there is very little dynamic action on the control voltage.
It seems 0.5MHz PFD is too low, but less clear if things improve as PFD rises, or if there are good and bad PFD values ?
Temperature will change the R's but not by huge amounts.
Temperature will be moving the VCO operating point slowly up, as the gates slow down needing a little more Vcc for the same MHz, That will change the loop-gain.
A spectrum plot of the VCO noise could help - ie is it random (likely dead-band issues), or some frequency peaks (loop stability?)
How proportional is that ? - is there a binary selection, meaning /8 thru /15 will have the same R, then /16 thru /31 have another R value etc.
Connecting a IT1602BC-12-33E-74.250000D oscillator would allow a PFD right up to 74.25MHz, and all proportional taps can be checked ?
Jmg, have you received your board, yet?
If you use your scope and look at the signal maybe 1ms after triggering on a rise, you will see what kind of long-term jitter exists at different settings.
Yes, it will be a challenge to get enough zoom. eg 10ns scope capture is only going to resolve just over 1000 steps in horizontal axis.
A 1ns scope might be good enough ?
Is the jitter even over the screen, or favouring the right side, or more area based - you mentioned a pie-shape ? Can you post a photo, with area mark-ups ?
The signal is much more square without the monitor connected BTW...
15;115
7;52
4;30
all seem to work OK. As if the ratio of these numbers is good...
30;223 is not as good, but also OK
What were the settings for those 2 captures ?
I was meaning the P2 PFD settings, the photos seem to be called IMG_1316.JPG, and have no P2 setting info ?
The last one has the lowest PFD frequency, at 666kHz just above the 500kHz that was not good.
Those give
30*20/4 = 150 MHz PFD = 5MHz
52*20/7 = 148.571MHz PFD = 2.86MHz
115*20/15 = 153.333' MHz PFD=1.333'MHz
223*20/30 = 148.666MHz PFD=666kHz
Thanks, if we suppose the PLL R's are binary switched, that suggests >= 32 is a problem. - a combination of less frequent PFD updates, and change in R ?
Other test points could be
148.5/(20/16) = 118.8 => try 16 & 119
148.5/(20/31) = 230.175 => 31 & 230
and a close to correct value, bumped >= 32 is
148.5/(20/33) = 245.025 => try 33 & 245
That last one is in the same band as /40, so should be poor too ?
So, XDIV decides the PLL frequency, right? What is the allowable range?
I think XMUL multiplies this to give VCO frequency that should be between 100 and 300 MHz.
BTW: I don't see the utility of the XDIVP when VCO is limited to 100 to 300 MHz... Am I missing something? Maybe for low power standby?
XDIV=2, XMUL=15 also looks good. Monitor says 61 Hz.
XDIV=3, XMUL=20 also looks OK, like the above. Monitor says 54 Hz. But, I think I do actually see some imperfections in the display when it is close to all white. Not horrible though.