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New streamer ADC input modes — Parallax Forums

New streamer ADC input modes

cgraceycgracey Posts: 14,134
in Propeller 2
I was thinking how we can stream data out DACs, but not ADC data in. I will augment the streamer's WFxxxx modes to sum IN data from ADCs, so that we can have automated high-speed data acquisition.

Streamer WFxxxx new modes sum ADC signals and write them:

WFLONG
8 ch into 8 nibs, up to 15 clocks per sample
4 ch into 4 bytes, up to 255 clocks per sample
2 ch into 2 words, up to 65535 clocks per sample
1 ch into 1 long, up to max clocks per sample

WFWORD
4 ch into 4 nibs
2 ch into 2 bytes
1 ch into 1 word

WFBYTE
2 ch into 2 nibs
1 ch into 1 byte

Comments

  • cgraceycgracey Posts: 14,134
    edited 2018-10-27 08:54
    At 225MHz, the 8-channel mode could convert 8 ADC pins into concurrent 4-bit samples at 15MHz. Or into 3-bit samples at 32MHz.
  • jmgjmg Posts: 15,171
    So this is like an ADC DMA, where the COG 'sets and forgets' ?
    Does this auto-wrap ?
  • cgraceycgracey Posts: 14,134
    jmg wrote: »
    So this is like an ADC DMA, where the COG 'sets and forgets' ?
    Does this auto-wrap ?

    Yes and yes.
  • TubularTubular Posts: 4,696
    nifty!
  • cgraceycgracey Posts: 14,134
    I don't think we'd need a 32-bit sum mode. 16-bit would be the practical limit.
  • Roy ElthamRoy Eltham Posts: 3,000
    This is DELUXE! I imagine some interesting DSP like things.... delays and reverbs will be trivial.
  • cgraceycgracey Posts: 14,134
    I think it could digitize NTSC in the background. I wonder how decent it would look played back.
  • cgraceycgracey Posts: 14,134
    Imagine if we had flash converters in every pin. High speed data acquisition would really be fantastic.
  • cgraceycgracey Posts: 14,134
    edited 2018-10-27 09:10
    I wonder, if we even had 4-bit flash converters, what higher resolution we could achieve through oversampling.
  • jmgjmg Posts: 15,171
    cgracey wrote: »
    I don't think we'd need a 32-bit sum mode. 16-bit would be the practical limit.

    Does it cost much to add 32b ?
    I've got some external integrator ideas, that should push well past 16 bits ... (P2 is purely digital)
    In this case, the capture result would need to stream, but I think that's the same pathway as ADC ?
  • cgraceycgracey Posts: 14,134
    jmg wrote: »
    cgracey wrote: »
    I don't think we'd need a 32-bit sum mode. 16-bit would be the practical limit.

    Does it cost much to add 32b ?
    I've got some external integrator ideas, that should push well past 16 bits ... (P2 is purely digital)
    In this case, the capture result would need to stream, but I think that's the same pathway as ADC ?

    Yes, the stream comes through the IN bit.
  • jmgjmg Posts: 15,171
    re-reading these 2 posts
    cgracey wrote: »
    I don't think we'd need a 32-bit sum mode. 16-bit would be the practical limit.
    cgracey wrote: »
    I will augment the streamer's WFxxxx modes to sum IN data from ADCs, so that we can have automated high-speed data acquisition.

    Streamer WFxxxx new modes sum ADC signals and write them:

    WFLONG
    ...
    1 ch into 1 long, up to max clocks per sample

    I think that's saying the 32b capture is already in there ? In that case. I'd keep it, for > 16b cases, even if all 32b are not useful, more than 16b could easily be.
  • YanomaniYanomani Posts: 1,524
    edited 2018-10-27 09:52
    cgracey wrote: »
    I wonder, if we even had 4-bit flash converters, what higher resolution we could achieve through oversampling.

    This means doing some redesign at the level of the pad ring, or I'm losing something?

    At the present design (the one we already have), have you resorted to any ONC18: G/MS available Deep N-well features, for noise isolation at the most sensitive analog areas?
  • cgraceycgracey Posts: 14,134
    jmg wrote: »
    re-reading these 2 posts
    cgracey wrote: »
    I don't think we'd need a 32-bit sum mode. 16-bit would be the practical limit.
    cgracey wrote: »
    I will augment the streamer's WFxxxx modes to sum IN data from ADCs, so that we can have automated high-speed data acquisition.

    Streamer WFxxxx new modes sum ADC signals and write them:

    WFLONG
    ...
    1 ch into 1 long, up to max clocks per sample

    I think that's saying the 32b capture is already in there ? In that case. I'd keep it, for > 16b cases, even if all 32b are not useful, more than 16b could easily be.

    I will implement the 32-bit mode, also.
  • cgraceycgracey Posts: 14,134
    edited 2018-10-27 17:15
    Yanomani wrote: »
    cgracey wrote: »
    I wonder, if we even had 4-bit flash converters, what higher resolution we could achieve through oversampling.

    This means doing some redesign at the level of the pad ring, or I'm losing something?

    At the present design (the one we already have), have you resorted to any ON C18: G/MS available Deep N-well features, for noise isolation at the most sensitive analog areas?

    Each pad has one giant deep N-well for all the 3.3V circuitry. I wonder if it would be good to divide that wells up, in order to isolate things like the ADC.
  • msrobotsmsrobots Posts: 3,709
    this may make it possible that one COG streams Data in the HUB another COG manipulates it and a third could stream it out continiously?
    Or is there just one streamer for all COGs?

    curious,

    Mike
  • cgraceycgracey Posts: 14,134
    msrobots wrote: »
    this may make it possible that one COG streams Data in the HUB another COG manipulates it and a third could stream it out continiously?
    Or is there just one streamer for all COGs?

    curious,

    Mike

    Every cog has a streamer.
  • potatoheadpotatohead Posts: 10,261
    edited 2018-10-27 19:24
    Roy is right, DELUXE!

    Chip, I was right. Amiga of microcontrollers. The stuff people are going to do with this thing! (I got plans, who doesn't?)

    Can't wait to see all that happen.

    Re: super fast 4 bit oversampling. From what I read, doing that needs some white noise, and or imperfection in the ADC to actualuze improved resolution. There has to be something to average.

  • jmgjmg Posts: 15,171
    cgracey wrote: »
    Streamer WFxxxx new modes sum ADC signals and write them:

    WFLONG
    8 ch into 8 nibs, up to 15 clocks per sample
    4 ch into 4 bytes, up to 255 clocks per sample
    2 ch into 2 words, up to 65535 clocks per sample
    1 ch into 1 long, up to max clocks per sample

    Thinking about uses for this, those 'up to' mean you could stream bytes, but have 5 or 6 valid bits, with 32/64 sysclks pacing ?

    How does the ADC itself behave at these high sample rates ?

    It seems there will be some slew-rate spec in there, meaning you cannot take 2 x 4 or 5 bit samples, and expect them to read opposite rails instantly.
    That slew will be C-sample and Current Source related.
    What is the low-bit-numbers slew rate ?
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