P2 FPGA: why does VGA only work in COG 0?
ersmith
Posts: 6,039
in Propeller 2
I presume I'm doing something wrong here, but I can only get VGA output to work if I drive the VGA from COG 0 (this is on my DE2-115 with the v32i FPGA image). The DE2-115 does have 4 cogs, and I can run code in the other COGs, but if I try to run the VGA code in anything other than COG 0 the monitor doesn't detect the signal.
I've attached the code below: it's a simple modification of Chip's VGA_640_x_480_8bpp.spin2. I changed to 4 bits per pixel to free up some RAM and moved the frame buffer from $1000 to $8000. As posted below, with the VGA in COG 0 and a simple line drawing routine in COG 2, everything works and I see a fat line sweeping across the screen. If I change the line commented with FIXME so that the VGA runs in COG 1, the monitor doesn't sync.
Have I missed something in the docs regarding the streamer? Is it only implemented on COG 0 in the FPGA?
Thanks for any insights,
Eric
I've attached the code below: it's a simple modification of Chip's VGA_640_x_480_8bpp.spin2. I changed to 4 bits per pixel to free up some RAM and moved the frame buffer from $1000 to $8000. As posted below, with the VGA in COG 0 and a simple line drawing routine in COG 2, everything works and I see a fat line sweeping across the screen. If I change the line commented with FIXME so that the VGA runs in COG 1, the monitor doesn't sync.
Have I missed something in the docs regarding the streamer? Is it only implemented on COG 0 in the FPGA?
Thanks for any insights,
Eric
'****************************** '* VGA 640 x 480 x 4bpp-lut * '****************************** CON intensity = 80 '0..128 fclk = 80_000_000.0 fpix = 25_000_000.0 fset = (fpix / fclk * 2.0) * float($4000_0000) vsync = 0 'vsync pin (all FPGA boards now) DAT org ' ' ' Setup ' entry ' hubset #$ff ' done for us in startup code mov x, #0 mov y, #0 rep @.end,#$100 wrlut y,x add y,##$11111100 add x,#1 .end rdfast ##(640*480)/(2*64),screenptr 'set rdfast to wrap on bitmap setxfrq ##round(fset) 'set transfer frequency to 25MHz 'the next 4 lines may be commented out to bypass level scaling setcy ##intensity << 24 'r set colorspace for rgb setci ##intensity << 16 'g setcq ##intensity << 08 'b setcmod #%01_0_000_0 'enable colorspace conversion wrpin dacmode,#0 'enable dac modes in pins 0..3 wrpin dacmode,#1 wrpin dacmode,#2 wrpin dacmode,#3 ' ' ' Field loop ' field mov x,#33 'top blanks call #blank mov x,#480 'set visible lines line call #hsync 'do horizontal sync xcont m_rf,#0 'visible line djnz x,#line 'another line? mov x,#10 'bottom blanks call #blank drvnot #vsync 'sync on mov x,#2 'sync blanks call #blank drvnot #vsync 'sync off jmp #field 'loop ' ' ' Subroutines ' blank call #hsync 'blank lines xcont m_vi,#0 _ret_ djnz x,#blank hsync xcont m_bs,#0 'horizontal sync xcont m_sn,#1 _ret_ xcont m_bv,#0 ' ' ' Initialized data ' dacmode long %0000_0000_000_1010000000000_01_00000_0 m_bs long $CF000000+16 'before sync m_sn long $CF000000+96 'sync m_bv long $CF000000+48 'before visible m_vi long $CF000000+640 'visible m_rf long $6F000000+640 'visible rlong 4bpp lut screenptr long $8000 x res 1 y res 1 ' ' ' Bitmap ' VAR long cog long stack[64] PUB demo | base, linesize, x, y coginit(2, runline, @stack[0]) coginit(0, @entry, 0) '' FIXME: why must this be cog 0?? repeat PUB runline | base, linesize, x, y base := $8000 ' screen memory linesize := 320 x := 1 repeat repeat y from 0 to 479 byte[base + y * linesize + x] := $ff byte[base + y * linesize + x-1] := $0 x++ if x => 300 x := 1
Comments
Ah, bummer, Thanks for the info, Dave!
Eric
So, it's a bit of a hack...
The P123 board has two VGA ports, so I bet one is wired to cog0 and the other to cog1...
I need to read the docs again to refresh my memory, been a while...
IIRC the A7 had separate load signals whereas the A9 had a single load signal that was inverted to the second DAC.
This was because the A9 has more power pins than the A7 so some IO was sacrificed.
AFAIK the second video DACS were never implemented.
Yeah, we didn't vote for "change".