How many PCB's are available (if any) for us mere mortals (those on the second list)?
I think we have around 120 planned for production. There should be enough for everybody, based on the list of forum members I've seen circulated who have expressed interest.
I think we have around 120 planned for production. There should be enough for everybody, based on the list of forum members I've seen circulated who have expressed interest.
Ken Gracey
Based on all the results I've saw to date, there should be some not so silent competition going on.
Kind of "Who in the whole world did the fanciest P2-enabled board?". :-D
Peter was nice enough to give away a bunch of his P2D2 boards. Are there going to be any P2 chips from this batch available for purchase to populate these boards? I know Peter was sent a bunch of P2 chips but I think those are for his rev B P2D2 boards.
Peter was nice enough to give away a bunch of his P2D2 boards. Are there going to be any P2 chips from this batch available for purchase to populate these boards? I know Peter was sent a bunch of P2 chips but I think those are for his rev B P2D2 boards.
It probably makes the most sense logistically/yields/speed to put all those on rev H/I?/J?, with the improvements, and do a single pick and place setup.
Not sure if P2D2x were going to be 4 layer ? - that was talked about, and it seems a good idea for any early-eval board to be (very) conservative in design.
You want any limits/issues to be in the silicon itself, not in the layout/cooling/ratings.
Cost-downs can always come along later for higher volumes...
Anyone with an older P2D2 could still put a production P2 on to them later.
Peter was nice enough to give away a bunch of his P2D2 boards. Are there going to be any P2 chips from this batch available for purchase to populate these boards? I know Peter was sent a bunch of P2 chips but I think those are for his rev B P2D2 boards.
Chip has indicated 15 P2 chips will go to Peter. The rest will be on Propeller 2 Evaluation Boards.
Peter was nice enough to give away a bunch of his P2D2 boards. Are there going to be any P2 chips from this batch available for purchase to populate these boards? I know Peter was sent a bunch of P2 chips but I think those are for his rev B P2D2 boards.
It probably makes the most sense logistically/yields/speed to put all those on rev H/I?/J?, with the improvements, and do a single pick and place setup.
Not sure if P2D2x were going to be 4 layer ? - that was talked about, and it seems a good idea for any early-eval board to be (very) conservative in design.
You want any limits/issues to be in the silicon itself, not in the layout/cooling/ratings.
Cost-downs can always come along later for higher volumes...
Anyone with an older P2D2 could still put a production P2 on to them later.
I think Peter is building one chip on the current P2D2 to send to ozpropdev/tubular/rogloh for comparison with the early proto chips packaged by OnSemi and on the original P2D2.
We will wait another week or so for the second rev of P2D2. No point in making it 4 layer as we want to see what P2 can do.
There is the monstrous Parallax board for other testing.
IMHO if 4 layer ends up being a requirement, or fan and/or heatsink for normal operation then P2's market will be severely reduced. I expect, and hope, these will not be normal requirements. I have my external fan and power supply on standby, should that be the case
... No point in making it 4 layer as we want to see what P2 can do.
I am all for 'seeing what P2 can do', but first step should be to actually see what the engineering samples silicon can do, then you can start doing things like removing layers, lowering regulator ratings, and see how cheap you can run in a more average application.
Compromise things too early, and you are never quite sure which limit you are hitting.
IMHO if 4 layer ends up being a requirement, or fan and/or heatsink for normal operation then P2's market will be severely reduced. I expect, and hope, these will not be normal requirements. I have my external fan and power supply on standby, should that be the case
Clearly, 4 layer is not a requirement, as P2 is operating on 2 layers right now.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Solutions to that are many, one is to spread the heat (4 layers is a low cost way to do that) or add heatsinks and more active cooling.
How much of that is needed, depends on the users final design, and their MHz expectations.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Aren't the thermal challenges only present when you overclock the P2? They aren't present with standard 180mhz operation are they?
... No point in making it 4 layer as we want to see what P2 can do.
I am all for 'seeing what P2 can do', but first step should be to actually see what the engineering samples silicon can do, then you can start doing things like removing layers, lowering regulator ratings, and see how cheap you can run in a more average application.
Compromise things too early, and you are never quite sure which limit you are hitting.
IMHO if 4 layer ends up being a requirement, or fan and/or heatsink for normal operation then P2's market will be severely reduced. I expect, and hope, these will not be normal requirements. I have my external fan and power supply on standby, should that be the case
Clearly, 4 layer is not a requirement, as P2 is operating on 2 layers right now.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Solutions to that are many, one is to spread the heat (4 layers is a low cost way to do that) or add heatsinks and more active cooling.
How much of that is needed, depends on the users final design, and their MHz expectations.
If you only build a tank, you will never know if a truck will do the job. Infinitely better to build both if you have the resources.
Sticking your head in the sand and requiring the tank doesn't let you discover why the tank is required, and therefore how you can avoid the tank design.
BTW you missed the memo. While the P2 runs hot (to touch, so subjective), the problem was in the PLL.
We have seen the ADC play out to be a silicon issue, but miss-directed software solutions distracted all from the real problem.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Aren't the thermal challenges only present when you overclock the P2? They aren't present with standard 180mhz operation are they?
See Cluso99's tests around 148.5MHz VGA operation. Those bench tests nicely show the thermal challenges...
BTW you missed the memo. While the P2 runs hot (to touch, so subjective), the problem was in the PLL.
? You seem to be reinforcing my point.
It does not matter what part of P2 has issues with temperature, as it is all inside the one package and users cannot change that, all they can do is exactly what you did, and that is cool the part better.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Aren't the thermal challenges only present when you overclock the P2? They aren't present with standard 180mhz operation are they?
See Cluso99's tests around 148.5MHz VGA operation. Those bench tests nicely show the thermal challenges...
BTW you missed the memo. While the P2 runs hot (to touch, so subjective), the problem was in the PLL.
? You seem to be reinforcing my point.
It does not matter what part of P2 has issues with temperature, as it is all inside the one package and users cannot change that, all they can do is exactly what you did, and that is cool the part better.
You certainly missed the memo!
I am NOT cooling the chip/board. Our ambient is 25C and rising. The board works fine with the PLL settings recommended by Chip.
AFAIK, none of the P2D2 working boards have any cooling attached for normal testing (the Melbourne guys did some ice testing though) and they are regularly overclocking.
However, the point is that the silicon design needs checking to see why the P2 wastes so much power when most of the silicon is not in used. It has NOT been proven to be a gated clocking issue!!! And I bet it's not the actual problem, but one of shutting down the blocks when not in use.
The board works fine with the PLL settings recommended by Chip.
You mean raising the PFD frequency ? ( which merely increased the temperature where this issue appears ? )
Placing such a constraint on PFD frequency, is not going to go down well with many users, and is more a workaround, than a solution.
The sample size here is very small, we do not know yet if your P2 was a good one, or a bad one, or merely average.
Maybe better decoupling of the PLL pin will help, or a separate PLL regulator ? There is not much externally that can be done here.
Temperature certainly seems to be a common trigger element here.
Better measurements of PLL jitter vs PFD vs temperature will likely help define this.
On the temperature thing, hang on a few days and we should have some better data with the final packaged chips
*very* roughly, the P2 dissipates around 1.2 watts when running around rated clock. This is similar to raspberry pi B+ (or 2)
Without any cooling, that causes a temp rise around 35 C
The board works fine with the PLL settings recommended by Chip.
You mean raising the PFD frequency ? ( which merely increased the temperature where this issue appears ? )
Placing such a constraint on PFD frequency, is not going to go down well with many users, and is more a workaround, than a solution.
The sample size here is very small, we do not know yet if your P2 was a good one, or a bad one, or merely average.
Maybe better decoupling of the PLL pin will help, or a separate PLL regulator ? There is not much externally that can be done here.
Temperature certainly seems to be a common trigger element here.
Better measurements of PLL jitter vs PFD vs temperature will likely help define this.
Maybe if you read the posts instead of asking so many questions, you would have seen the solution. To save you sifting thru the thread filled with your posts (hint hint), changing the clock divider and multipliers as suggested by Chip, and still at 148.5MHz, jitter was cured.
Maybe if you read the posts instead of asking so many questions, you would have seen the solution. To save you sifting thru the thread filled with your posts (hint hint), changing the clock divider and multipliers as suggested by Chip, and still at 148.5MHz, jitter was cured.
There are tradeoffs with those other figures. There will always be jitter, the monitors smooth it out to varying degrees
I'm re currently making a better vga test setup, using a 1 to 8 VGA amplifier (Altronics), so we can send the same signal to a whole range of monitors and check the results simultaneously.
One of my monitors is an Acer, and while your settings are great for that monitor Cluso, on another monitor it wraps a portion of the video onto the next line.
We still have a way to go to find optimal settings
Maybe if you read the posts instead of asking so many questions,
Sound advice, try it yourself one day, given I already mentioned exactly the PFD change above, in the post you quoted !
'cured' is a creative word for what changed....
I'm running 240MHz all day long on a two-layer P2D2 board and I've had no problems. The chip is rather warm to the touch, but I wouldn't call it hot. Here is my setup:
So I've read through this entire thread and I'm not sure if I just missed it or if it hasn't been mentioned, but what will the cost of these boards be? I'm super excited to get my hands on one of these!!!
So I've read through this entire thread and I'm not sure if I just missed it or if it hasn't been mentioned, but what will the cost of these boards be? I'm super excited to get my hands on one of these!!!
The initial production is going fair. We received some parts in tubes instead of reels and didn't have all the feeders for the components. It's typical production-startup headaches and they're quite small considering the short timeline between finishing the bill of materials, getting parts, and actually programming the pick-and-place. Our team does very well and has a lot of experience working together, so nothing really slows us down all that much.
When Chip arrives tomorrow we may be able to hand him a P2 Evaluation Board.
Comments
How many PCB's are available (if any) for us mere mortals (those on the second list)?
I think we have around 120 planned for production. There should be enough for everybody, based on the list of forum members I've seen circulated who have expressed interest.
Ken Gracey
Did you used the Egg Beater to rotate them???
Henrique
Based on all the results I've saw to date, there should be some not so silent competition going on.
Kind of "Who in the whole world did the fanciest P2-enabled board?". :-D
It probably makes the most sense logistically/yields/speed to put all those on rev H/I?/J?, with the improvements, and do a single pick and place setup.
Not sure if P2D2x were going to be 4 layer ? - that was talked about, and it seems a good idea for any early-eval board to be (very) conservative in design.
You want any limits/issues to be in the silicon itself, not in the layout/cooling/ratings.
Cost-downs can always come along later for higher volumes...
Anyone with an older P2D2 could still put a production P2 on to them later.
Chip has indicated 15 P2 chips will go to Peter. The rest will be on Propeller 2 Evaluation Boards.
Ken Gracey
We expect 120 PCBs to be built up. Some will be kept inside Parallax (maybe 6-8?) but the rest are for all of you.
Ken Gracey
We will wait another week or so for the second rev of P2D2. No point in making it 4 layer as we want to see what P2 can do.
There is the monstrous Parallax board for other testing.
IMHO if 4 layer ends up being a requirement, or fan and/or heatsink for normal operation then P2's market will be severely reduced. I expect, and hope, these will not be normal requirements. I have my external fan and power supply on standby, should that be the case
Compromise things too early, and you are never quite sure which limit you are hitting.
Clearly, 4 layer is not a requirement, as P2 is operating on 2 layers right now.
However, P2 is also clearly a thermal challenge, with MHz abilities above expected which also means cooling challenges.
Your own tests have shown that.
Solutions to that are many, one is to spread the heat (4 layers is a low cost way to do that) or add heatsinks and more active cooling.
How much of that is needed, depends on the users final design, and their MHz expectations.
If you only build a tank, you will never know if a truck will do the job. Infinitely better to build both if you have the resources.
Sticking your head in the sand and requiring the tank doesn't let you discover why the tank is required, and therefore how you can avoid the tank design.
BTW you missed the memo. While the P2 runs hot (to touch, so subjective), the problem was in the PLL.
We have seen the ADC play out to be a silicon issue, but miss-directed software solutions distracted all from the real problem.
See Cluso99's tests around 148.5MHz VGA operation. Those bench tests nicely show the thermal challenges...
? You seem to be reinforcing my point.
It does not matter what part of P2 has issues with temperature, as it is all inside the one package and users cannot change that, all they can do is exactly what you did, and that is cool the part better.
You certainly missed the memo!
I am NOT cooling the chip/board. Our ambient is 25C and rising. The board works fine with the PLL settings recommended by Chip.
AFAIK, none of the P2D2 working boards have any cooling attached for normal testing (the Melbourne guys did some ice testing though) and they are regularly overclocking.
However, the point is that the silicon design needs checking to see why the P2 wastes so much power when most of the silicon is not in used. It has NOT been proven to be a gated clocking issue!!! And I bet it's not the actual problem, but one of shutting down the blocks when not in use.
hehe, you mean this memo ? - your own, I believe !
Cluso99 : " I am only running 2 cogs at 148.5MHz and it gets hot and starts to jitter fairly quickly which isn’t good. "
I agree that 'gets hot and starts to jitter fairly quickly' is not good.
You mean raising the PFD frequency ? ( which merely increased the temperature where this issue appears ? )
Placing such a constraint on PFD frequency, is not going to go down well with many users, and is more a workaround, than a solution.
The sample size here is very small, we do not know yet if your P2 was a good one, or a bad one, or merely average.
Maybe better decoupling of the PLL pin will help, or a separate PLL regulator ? There is not much externally that can be done here.
Temperature certainly seems to be a common trigger element here.
Better measurements of PLL jitter vs PFD vs temperature will likely help define this.
*very* roughly, the P2 dissipates around 1.2 watts when running around rated clock. This is similar to raspberry pi B+ (or 2)
Without any cooling, that causes a temp rise around 35 C
There are tradeoffs with those other figures. There will always be jitter, the monitors smooth it out to varying degrees
I'm re currently making a better vga test setup, using a 1 to 8 VGA amplifier (Altronics), so we can send the same signal to a whole range of monitors and check the results simultaneously.
One of my monitors is an Acer, and while your settings are great for that monitor Cluso, on another monitor it wraps a portion of the video onto the next line.
We still have a way to go to find optimal settings
Sound advice, try it yourself one day, given I already mentioned exactly the PFD change above, in the post you quoted !
'cured' is a creative word for what changed....
Microcontroller should not have fans (IMHO)...
The 4 layer Eval Board, with 3oz bottom layer, should be very good example, tho it's probably a larger 'working area' than most users would target.
Taking care to reduce losses in the regulators will also lower the total thermal burden. (lower Rds FETs, lower ESR inductor etc)
HAHAHAHA!!!!
I just lol'ed
$150.000000000, to be precise.
When Chip arrives tomorrow we may be able to hand him a P2 Evaluation Board.
Ken Gracey
Ken Gracey