- Can you explain me how 600mA will flow, If i use 10R.
(i,e) I = V/R
= 12v/10 = 1.2A
correct me friend if i am wrong.
Well, it obviously is a dynamic current so there is no single figure. I guess an average could be estimated but my target area was the part I'd highlighted as the voltage of the gate, Vgs, during load switching. This will be the gate drive's longest, and most important, part of switching. Most important because this is the unwanted linear part of switching ... which is where large heating of the powerMOS occurs.
I'd used Vgs of 5 volts in my guesstimate but 4 or 4.5 volts might be more accurate. Only using a scope to look at the signal will know this voltage for sure. Anything down to gate threshold is possible I guess.
I took a volt off the 12 volt drive supply for drive output voltage, so 11 volts there. That leaves (11-5)/10 = 0.6
Yes, it's a dynamic current and no doubt highly non-linear. Is it even possible to calculate current over time during transitions to any reasonable degree of accuracy? I wonder what a SPICE simulation would say about it.
We need the fastest possible gate capacitance charge discharge time so as to achieve efficiency and run cool. Hence the need for a good gate driver and low inductance circuit layout etc.
Edit: Hmm...What I said above seems rather contrary. I said "highly non-linear" which I'm sure is true but at the same time the MOSFET is operating in what is often called it's "linear region" during a transition. Not that MOSFETs are actually not very linear anywhere in their characteristics.
Budd,
If you are looking at new scopes, make sure it has four analogue channels. Two channels are only good for freebies, imho. Even more would be cool but the price rockets above four.
Capture memory size is another important feature to look for, 100k samples/channel would be absolute minimum. 1M/ch is much nicer.
There's a whole lot of sampling quality factors too but easiest just to look for online reviews to decide on product quality.
Yes, it's a dynamic current and no doubt highly non-linear. Is it even possible to calculate current over time during transitions to any reasonable degree of accuracy? I wonder what a SPICE simulation would say about it.
We need the fastest possible gate capacitance charge discharge time so as to achieve efficiency and run cool. Hence the need for a good gate driver and low inductance circuit layout etc.
Edit: Hmm...What I said above seems rather contrary. I said "highly non-linear" which I'm sure is true but at the same time the MOSFET is operating in what is often called it's "linear region" during a transition. Not that MOSFETs are actually not very linear anywhere in their characteristics.
It is non-linear since you are charging and discharging the gate capacitor through whatever resistance and inductance the circuit traces and components present. Not an easy task to simulate since the changing voltage and current also affects the gate capacitance as well. Best approximation is probably to assume an RC circuit as long as the layout is good and the inductance is low.
PS, rather than thinking of the region between the MOSFET being fully on or fully off as the "linear" region I consider it to be the active region, and reserve "linear region" for the linear gain region of both mosfets and bipolar transistors used in audio and other analog applications. Could also consider it the transition region I suppose.
The interesting thing about this circuit is that it has been around for several years yet the original article by Bilal on microcontrollerslab.com never actually shows any hardware and how it performs, just the schematic. Elsewhere some other guy explains why the circuit gets hot and doesn't work properly because of shoot-through and a 10us delay circuit is necessary but he wants everyone to pay to read his paper..... The interweb is full of "advice" but do they ever try out their own advice?
...make sure it has four analogue channels.Two channels are only good for freebies, imho...
Wow. For us old guys four channels is a luxury. We dreamed of two channels as kids. Or even just one.
The go to budget scope for the past couple of years has been the the Rigol DS1054Z. A four channel, 1GS/s, 50MHz bandwidth scope for a bit over 300 dollars.
The magic part of that machine is that it is the same as the 100MHz version which is a lot more expensive. With a bit of googling, "Rigol DS1054Z hack", one can find out how to convert the cheap 50MHz scope to a 100MHz with just a software key. Worked very nicely for me
@kwinn,
It is non-linear since you are charging and discharging the gate capacitor through whatever resistance and inductance the circuit traces and components present...
If it were just a case of resistance and inductance it would be a linear circuit we could analyse.
Not an easy task to simulate since the changing voltage and current also affects the gate capacitance as well.
That is the thing. The MOSFET gate capacitance is not linear. It changes with voltage.
Hmm...isn't that similar to what was called "Miller capacitance" of the grid inputs of vacuum tubes?
...reserve "linear region" for the linear gain region of both mosfets and bipolar transistors used in audio and other analog applications
There is no linear gain region of MOSFETs or bipolar transistors. Except, approximately, in a very small range of operation. They are horribly non-linear. The most linear gain devices ever are still vacuum tubes. Here we are slamming them from full on to full off, about as non-linear as one can get.
"transition region" sounds good. Point is that if an ideal MOSFET is totally off no current flows and heat generation is zero. Like an open circuit. If it is totally on then there is no voltage across it and heat generation is zero. Like a short circuit. Problem comes in the time between off and on during which the MOSFET acts like a resistor and generates lots of heat.
@Peter Jakacki,
...some other guy explains why the circuit gets hot and doesn't work properly because of shoot-through and a 10us delay circuit is necessary...
I was wondering about shoot-through.
No worries if the rise and fall times of the MOSFETS is zero. But that is physically impossible.
Looking at the datasheet for the IR2110 don't see anything to help with the shoot-through problem.
...make sure it has four analogue channels.Two channels are only good for freebies, imho...
Wow. For us old guys four channels is a luxury. We dreamed of two channels as kids. Or even just one.
The go to budget scope for the past couple of years has been the the Rigol DS1054Z. A four channel, 1GS/s, 50MHz bandwidth scope for a bit over 300 dollars.
The magic part of that machine is that it is the same as the 100MHz version which is a lot more expensive. With a bit of googling, "Rigol DS1054Z hack", one can find out how to convert the cheap 50MHz scope to a 100MHz with just a software key. Worked very nicely for me
@kwinn,
It is non-linear since you are charging and discharging the gate capacitor through whatever resistance and inductance the circuit traces and components present...
If it were just a case of resistance and inductance it would be a linear circuit we could analyse.
Not an easy task to simulate since the changing voltage and current also affects the gate capacitance as well.
That is the thing. The MOSFET gate capacitance is not linear. It changes with voltage.
Hmm...isn't that similar to what was called "Miller capacitance" of the grid inputs of vacuum tubes?
...reserve "linear region" for the linear gain region of both mosfets and bipolar transistors used in audio and other analog applications
There is no linear gain region of MOSFETs or bipolar transistors. Except, approximately, in a very small range of operation. They are horribly non-linear. The most linear gain devices ever are still vacuum tubes. Here we are slamming them from full on to full off, about as non-linear as one can get.
"transition region" sounds good. Point is that if an ideal MOSFET is totally off no current flows and heat generation is zero. Like an open circuit. If it is totally on then there is no voltage across it and heat generation is zero. Like a short circuit. Problem comes in the time between off and on during which the MOSFET acts like a resistor and generates lots of heat.
@Peter Jakacki,
...some other guy explains why the circuit gets hot and doesn't work properly because of shoot-through and a 10us delay circuit is necessary...
I was wondering about shoot-through.
No worries if the rise and fall times of the MOSFETS is zero. But that is physically impossible.
Looking at the datasheet for the IR2110 don't see anything to help with the shoot-through problem.
The shoot-through is more of a problem when two mosfets are connected in series as in each half of an H bridge. Then current can "shoot through" as one mosfet is turned on and the other one is turned off. That is usually dealt with by the gate drive circuitry turning one off a short time before the other one is turned on. Don't see any way the power mosfets can be made to do that individually. There is of course some additional current going through the mosfets and the load as they transition between on and off states, but that is relatively small. See this abstract for more info.
The shoot-through is more of a problem when two mosfets are connected in series as in each half of an H bridge.
I'm not sure I follow what you are saying. In the circuits presented in this thread that is exactly the configuration under consideration, two MOSFETs in series. Ergo I surmise shoot-through is a potential problem.
Looking at the IR2110 gate driver block diagram in the data sheet I see it has some flip-flops and a delay element included. It's not clear to me how that helps with any shoot-through issue (if there is one of course).
I'd be wanting assess that in an actual circuit and take care of the timing in whatever is driving the logic inputs to the IR2110. We have software control of that right.
I haven't put any effort into examining that side of things but there is ton=150 and toff=125, so turn-off lags are 25ns quicker than turn-on lags. That helps. And, with the gate series diode, the gate turn-off current is higher too. Not to mention FETs are a lot more forgiving around this issue.
There is a number of potential common mode transients possible in that circuit. One of them may involve moving R1 and D3 away from Q1 gate and put between Vs and the motor phase instead. ie: Sort of reinstating what I'd previously said to eliminate.
The whole bootstrapping mechanism is a bit vague for me. The IR2110 datasheet doesn't explain it at all.
It looks like the bootstrapping is contingent on maintaining a certain minimum percentage low-side on time. So can't do full 0% to 100% range of PWM. Not a problem in practise.
And best to power up by synchronously sequentially firing only low-sides for some cycles before going to live PWM. This allows unloaded power up sequence so permanent magnets won't experience any braking.
All quite doable but just some software details to get right.
- Can you explain me how 600mA will flow, If i use 10R.
(i,e) I = V/R
= 12v/10 = 1.2A
correct me friend if i am wrong.
Well, it obviously is a dynamic current so there is no single figure. I guess an average could be estimated but my target area was the part I'd highlighted as the voltage of the gate, Vgs, during load switching. This will be the gate drive's longest, and most important, part of switching. Most important because this is the unwanted linear part of switching ... which is where large heating of the powerMOS occurs.
I'd used Vgs of 5 volts in my guesstimate but 4 or 4.5 volts might be more accurate. Only using a scope to look at the signal will know this voltage for sure. Anything down to gate threshold is possible I guess.
I took a volt off the 12 volt drive supply for drive output voltage, so 11 volts there. That leaves (11-5)/10 = 0.6
Thank you for the explanation evanh, i have not measured the vgs. Because i not having scope(but i will get it soon).
- That is larger the vgs higher the current(for irf3205 it limits up-to +/-20v)
- nominally it will be 5v(vgs)
(i,e) For eg:
To switch vcc= 50 volt, Fets gate should be more than the vcc to switch. Say Fets gate=55v { 50 (switching volt) + 5 (vgs) }
Budd,
If you are looking at new scopes, make sure it has four analogue channels. Two channels are only good for freebies, imho. Even more would be cool but the price rockets above four.
Capture memory size is another important feature to look for, 100k samples/channel would be absolute minimum. 1M/ch is much nicer.
There's a whole lot of sampling quality factors too but easiest just to look for online reviews to decide on product quality.
To switch vcc= 50 volt, Fets gate should be more than the vcc to switch. Say Fets gate=55v { 50 (switching volt) + 5 (vgs) }
Voltage between VB (pin 6) and VS (pin 5) provides the supply for that. I'll label this VBS. C1 is the charge store for VBS. When Q1 is on, the voltage between VB and VSS equals VBS plus MOSV.
The "bootstrap" function is how C1 gets charged: Q2 pulls VS (pin 5) down to VSS, current then charges C1 through D1 from VCC (pin 3). Charge on C1 needs to be maintained by software.
So the VBS voltage is roughly VCC - 1 volt. I've assumed VCC to be 12 volts previously but could be from 10 to 15 volts.
PS: I'm reading all these labels from the first diagram, not the hand drawings.
Heater,
You did a Youtube search for the IR2110 didn't you. I see he covers exactly this part near the end.
Just to be picky I'll point out he's skimmed over a function in the IR2110 without really reading it. He quickly runs through each of the blocks in the functional diagram and comments on the job of each area. When he got to the pulse generator, pulse filter and latch he says it's for protection. Not the case at all.
I had to read the block diagram carefully myself before realising those particular blocks are solely about handling the extreme spec of high-side driver up to 500 volts without inductive nor capacitive coupling! To prevent problematic heating inside the IC it uses very short pulses to set and reset the latch for high-side driver.
To compensate for the resulting mismatched lags, the low-side circuit has a delay block inserted. This delay will be set, maybe even trimmed, to match the innate propagation time of the high-side circuit.
No, it's not a snoozer. I think Sam Ben-Yaakov's electronics vids are great. He has a lot more to explain about MOSFETs in other videos. I have a bad habit to start a video last thing at night, I'm usually asleep before the end.
Steady on there evanh. I have a long way to go before making a century.
Comments
I'd used Vgs of 5 volts in my guesstimate but 4 or 4.5 volts might be more accurate. Only using a scope to look at the signal will know this voltage for sure. Anything down to gate threshold is possible I guess.
I took a volt off the 12 volt drive supply for drive output voltage, so 11 volts there. That leaves (11-5)/10 = 0.6
We need the fastest possible gate capacitance charge discharge time so as to achieve efficiency and run cool. Hence the need for a good gate driver and low inductance circuit layout etc.
Edit: Hmm...What I said above seems rather contrary. I said "highly non-linear" which I'm sure is true but at the same time the MOSFET is operating in what is often called it's "linear region" during a transition. Not that MOSFETs are actually not very linear anywhere in their characteristics.
If you are looking at new scopes, make sure it has four analogue channels. Two channels are only good for freebies, imho. Even more would be cool but the price rockets above four.
Capture memory size is another important feature to look for, 100k samples/channel would be absolute minimum. 1M/ch is much nicer.
There's a whole lot of sampling quality factors too but easiest just to look for online reviews to decide on product quality.
It is non-linear since you are charging and discharging the gate capacitor through whatever resistance and inductance the circuit traces and components present. Not an easy task to simulate since the changing voltage and current also affects the gate capacitance as well. Best approximation is probably to assume an RC circuit as long as the layout is good and the inductance is low.
The go to budget scope for the past couple of years has been the the Rigol DS1054Z. A four channel, 1GS/s, 50MHz bandwidth scope for a bit over 300 dollars.
The magic part of that machine is that it is the same as the 100MHz version which is a lot more expensive. With a bit of googling, "Rigol DS1054Z hack", one can find out how to convert the cheap 50MHz scope to a 100MHz with just a software key. Worked very nicely for me
@kwinn, If it were just a case of resistance and inductance it would be a linear circuit we could analyse. That is the thing. The MOSFET gate capacitance is not linear. It changes with voltage.
Hmm...isn't that similar to what was called "Miller capacitance" of the grid inputs of vacuum tubes? There is no linear gain region of MOSFETs or bipolar transistors. Except, approximately, in a very small range of operation. They are horribly non-linear. The most linear gain devices ever are still vacuum tubes. Here we are slamming them from full on to full off, about as non-linear as one can get.
"transition region" sounds good. Point is that if an ideal MOSFET is totally off no current flows and heat generation is zero. Like an open circuit. If it is totally on then there is no voltage across it and heat generation is zero. Like a short circuit. Problem comes in the time between off and on during which the MOSFET acts like a resistor and generates lots of heat.
@Peter Jakacki, I was wondering about shoot-through.
No worries if the rise and fall times of the MOSFETS is zero. But that is physically impossible.
Looking at the datasheet for the IR2110 don't see anything to help with the shoot-through problem.
The shoot-through is more of a problem when two mosfets are connected in series as in each half of an H bridge. Then current can "shoot through" as one mosfet is turned on and the other one is turned off. That is usually dealt with by the gate drive circuitry turning one off a short time before the other one is turned on. Don't see any way the power mosfets can be made to do that individually. There is of course some additional current going through the mosfets and the load as they transition between on and off states, but that is relatively small. See this abstract for more info.
Looking at the IR2110 gate driver block diagram in the data sheet I see it has some flip-flops and a delay element included. It's not clear to me how that helps with any shoot-through issue (if there is one of course).
I'd be wanting assess that in an actual circuit and take care of the timing in whatever is driving the logic inputs to the IR2110. We have software control of that right.
There is a number of potential common mode transients possible in that circuit. One of them may involve moving R1 and D3 away from Q1 gate and put between Vs and the motor phase instead. ie: Sort of reinstating what I'd previously said to eliminate.
The whole bootstrapping mechanism is a bit vague for me. The IR2110 datasheet doesn't explain it at all.
And best to power up by synchronously sequentially firing only low-sides for some cycles before going to live PWM. This allows unloaded power up sequence so permanent magnets won't experience any braking.
All quite doable but just some software details to get right.
Thank you for the explanation evanh, i have not measured the vgs. Because i not having scope(but i will get it soon).
- That is larger the vgs higher the current(for irf3205 it limits up-to +/-20v)
- nominally it will be 5v(vgs)
(i,e) For eg:
To switch vcc= 50 volt, Fets gate should be more than the vcc to switch. Say Fets gate=55v { 50 (switching volt) + 5 (vgs) }
sure evahn
The "bootstrap" function is how C1 gets charged: Q2 pulls VS (pin 5) down to VSS, current then charges C1 through D1 from VCC (pin 3). Charge on C1 needs to be maintained by software.
So the VBS voltage is roughly VCC - 1 volt. I've assumed VCC to be 12 volts previously but could be from 10 to 15 volts.
PS: I'm reading all these labels from the first diagram, not the hand drawings.
You did a Youtube search for the IR2110 didn't you. I see he covers exactly this part near the end.
Just to be picky I'll point out he's skimmed over a function in the IR2110 without really reading it. He quickly runs through each of the blocks in the functional diagram and comments on the job of each area. When he got to the pulse generator, pulse filter and latch he says it's for protection. Not the case at all.
I had to read the block diagram carefully myself before realising those particular blocks are solely about handling the extreme spec of high-side driver up to 500 volts without inductive nor capacitive coupling! To prevent problematic heating inside the IC it uses very short pulses to set and reset the latch for high-side driver.
To compensate for the resulting mismatched lags, the low-side circuit has a delay block inserted. This delay will be set, maybe even trimmed, to match the innate propagation time of the high-side circuit.
Actually I missed the end of that video, skipping the IR2110 stuff. Must have dosed off.
Jim
Steady on there evanh. I have a long way to go before making a century.