Power Routing Troubles
threadz
Posts: 56
in Propeller 2
I've run into some difficulties when planning for integrating the Prop2 into a PCB when it comes out. Mainly, that if you want the IOs to use 3.3V or really any level besides 1.8V, you have to run two power traces around the IC.
One route can fit between the ground plate and the pins with no hassle. But the second power trace requires you to find a way to cram in a bunch of vias in addition to all the IOs traces and smoothing capacitors needed around the outside of the Prop. Also, connecting up the vias on the bottom layer of the PCB basically blocks off all of the space under the Prop from being used for routing on 2 layer boards.
So I guess my question here is do all of the VDD pins need to be routed to source power or are they internally connected enough for one or two of them to be enough? If they are, that would solve many a problem.
One route can fit between the ground plate and the pins with no hassle. But the second power trace requires you to find a way to cram in a bunch of vias in addition to all the IOs traces and smoothing capacitors needed around the outside of the Prop. Also, connecting up the vias on the bottom layer of the PCB basically blocks off all of the space under the Prop from being used for routing on 2 layer boards.
So I guess my question here is do all of the VDD pins need to be routed to source power or are they internally connected enough for one or two of them to be enough? If they are, that would solve many a problem.
Comments
How many fewer I dunno.
I think this can not be since it is supposed to be possible to run different groups of pins with different levels of Vdd. That would not work if they are connected internally.
Mike
Right, the IO_VDD that power the pins have to be connected cuz there individual. I'm talking about not connecting the VDD that powers the RAM and COGs and has to be 1.8v.
Although you could not connect IO_VDDs for groups of pins your not using. I think.... idk ask Chip.
I'm not sure, but this might entail a four-layer board to route the voltages that the P2 requires.
-Phil
http://forums.parallax.com/discussion/164364/prop2-family/p1
There is 4 Vdd's per side, 16 pins total. My gut feeling is that's way more than needed and Chip was just filling in space.
-Phil
Probably best established by doing a 4 layer PCB that does route every pin, and then doing a comparison with a cut-trace version to confirm.
ie I'd start P2 testing on a more conservative PCB design, then see how much is actually needed, once that is proven....
We've been through this already with the P1: missing power connections and/or insufficient bypassing have led to PLL failures.
I say, if you can't make all the connections and bypassing in two layers, you have no choice but to go to four.
-Phil
The big question is how many is he trying to do away with. I'm guessing he's wanting go below half.
Also, this seems like a problem most people will run into so if this issue can be addressed by changing the design it might be worth looking into while we have the chance.
And by we I mean not me. This is out of my depth. I just want the magic black sand brick to do math good.
http://forums.parallax.com/discussion/comment/1393527/#Comment_1393527
That suggests one VIO pin is used for the PLL_VDD filter, using a local follow-regulator and filtered Vdd_core feed.
Looks like an up to date pinout is needed, for the PAD Ring that is in the FAB now, that shows PLL power dependent pins ?
You could route using 0 ohm jumpers, which gives some trade off on layers-vs-BOM, and is also easy to remove/add for testing.
that's the perfect fix to my problem. because of how the vias are set up there's nothing right under the chip itself. I'm kinda disappointed in myself for not seeing it sooner it's like right there.
Weird question, is it possible to over-decouple? My gut says no but my gut also said other things that didn't go well
I would put a VIO power ring on one side of the PCB, inside the pins, and a VDD ring directly on the other side. For the ring on the bottom, you would need vias to get to the pins on top.
Some purists like to vary the decoupling caps, working on the theory that a smaller Cap has a higher series-resonant dip - I can believe that could matter in a RF design, but decoupling CMOS MCUs, I'm not sure that matters so much.
If you leave one cap not fitted, you can probe the internal Core Vdd, and see how that compares with the decoupled Vdd pin-signals.
-Phil
Somewhere around here I saw a discussion. If I remember correctly, Parallax is planning to short circuit problems like this by producing a P2 module, to which I would add a smiley face and name it a "minion."
(Kids will love it:)
I would expect this early in the process.
So, for low volumes, I think the design option to beat is doing it all yourself... and risking failure. OR design a board for your minion. Way more fun.
If its much bigger than that, close to the pins, eg 14x14mm, it doesn't leave much room for internal vias.
I've been using this strategy with the Max10, whose external pad is about 9x9mm
That doesn't really explain anything about VDD's needs.
I find it hard to believe the Prop2 will be drawing more than 1 Amp for max rating of VDD. Even 8 pins is overkill for that. I'm guessing it's more likely 500 mA is what you're aiming for. If every second VDD is connected all the way round ...
I meant the other side of the board. Sorry.
Look at this and go to the 14 x 14 mm 100-lead exposed-pad package. You can see that the bond pad is 10.3 x 10.3 mm:
https://www.amkor.com/go/packaging/all-packages/exposedpad-lqfp-/-tqfp/
All the GND pads on the die are connected to that exposed pad.
Without connecting all the VDD's, you will get local VDD drops on the internal power grid. I'm not sure how much current this thing will take. We'll know soon from the synthesis work.
So just follow proven engineering rules: do it right, do it right the first time and swamp the drains in a sea of c's. Clinton failed, Bush failed, and Obama failed. We won't fail if we follow Chips advice.
ErNa beat me to it. The only digital circuit designers are those that are designing RF circuits but don't know it
One might have a digital signal toggling at 1Hz and think that is such a low frequency that not much care need be taken with it.
But, the rise and fall times of such signals are very short. Those edges are well into the RF range. They can cause blips on the chips power supply. They can can cross talk into nearby signals.
Ignoring the analog and high speed nature of digital circuits can lead to all kind of intermittent errors and head scratching. I first became painfully aware of this back in the 1980's when I was assigned the task of fixing "software glitches" on a multi-processor system. After much investigation I turned to the back plane buss that tied it all together. It was only operating at 1MHz and not very long but there was ringing and cross talk all over the place. Worked most of the time but.... Cleaning that mess up got everything working reliably.
Chips have only gotten much faster since then!
As for over decoupling. I guess it can be done. If all your decoupling caps are 1 Farad super caps the power supply will die when you turn it on. Or the traces melt !
As for using different sizes and types of decoupling caps, we have to remember that a capacitor is not just a capacitor. It is also an inductor and resistor. All of which varies with frequency. Together with the impedance of your outputs, inductance and capacitance of your traces etc what we have is a horrible mess of analog circuitry, resonant circuits, etc. Most of which is still a black art to me...
- Connect all the VDD and VIOs
- Decouple with a few small SMD capacitors totaling a few microFarads.
- No supercaps
- No high speed or high current analog signals get near this IC because black magic
- Pray
However, just in case that does not work, it's best to employ sound engineering techniques. Even if one is not totally clear on the theory behind it. Then I'm sure the P2 will fly every time.
Often companies produce reference designs for their chips. Including PCB layout around the pins, power distribution and decoupling where these things are critical. No doubt the first P2 boards from Parallax will show the way to go.
Yes, when in doubt just copy what works.
Monkey see, monkey do, monkey don't need to understand.