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Power Routing Troubles — Parallax Forums

Power Routing Troubles

threadzthreadz Posts: 56
in Propeller 2
I've run into some difficulties when planning for integrating the Prop2 into a PCB when it comes out. Mainly, that if you want the IOs to use 3.3V or really any level besides 1.8V, you have to run two power traces around the IC.
One route can fit between the ground plate and the pins with no hassle. But the second power trace requires you to find a way to cram in a bunch of vias in addition to all the IOs traces and smoothing capacitors needed around the outside of the Prop. Also, connecting up the vias on the bottom layer of the PCB basically blocks off all of the space under the Prop from being used for routing on 2 layer boards.

So I guess my question here is do all of the VDD pins need to be routed to source power or are they internally connected enough for one or two of them to be enough? If they are, that would solve many a problem.

Comments

  • evanhevanh Posts: 15,915
    Vdd pins are all connected in a ring as part of the custom layout. An even spread of connections to fewer pins would most likely be fine. It's not like the Prop2 is a hog.

    How many fewer I dunno.
  • msrobotsmsrobots Posts: 3,709
    evanh wrote: »
    Vdd pins are all connected in a ring as part of the custom layout. An even spread of connections to fewer pins would most likely be fine. It's not like the Prop2 is a hog.

    How many fewer I dunno.

    I think this can not be since it is supposed to be possible to run different groups of pins with different levels of Vdd. That would not work if they are connected internally.

    Mike

  • SeairthSeairth Posts: 2,474
    This does not seem like an acceptable solution. If that many Vdd pins are part of the design, shouldn't they all be connectedl?
  • threadzthreadz Posts: 56
    edited 2017-10-02 00:33
    msrobots wrote: »
    I think this can not be since it is supposed to be possible to run different groups of pins with different levels of Vdd. That would not work if they are connected internally.

    Right, the IO_VDD that power the pins have to be connected cuz there individual. I'm talking about not connecting the VDD that powers the RAM and COGs and has to be 1.8v.

    Although you could not connect IO_VDDs for groups of pins your not using. I think.... idk ask Chip.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2017-10-02 01:56
    Even if power pins are connected internally, it's never a good idea not to connect them externally as well. Think about the fine gold wires and fragile internal traces compared to how hurky a PCB trace can be. An interstate (PCB trace) can carry much more traffic (current) than a side street (internal trace).

    I'm not sure, but this might entail a four-layer board to route the voltages that the P2 requires.

    -Phil
  • evanhevanh Posts: 15,915

    http://forums.parallax.com/discussion/164364/prop2-family/p1

    There is 4 Vdd's per side, 16 pins total. My gut feeling is that's way more than needed and Chip was just filling in space.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    evanh wrote:
    My gut feeling is that's way more than needed and Chip was just filling in space.
    That's not an assumption that I'd be willing to make when laying out a board.

    -Phil
  • jmgjmg Posts: 15,173
    threadz wrote: »
    So I guess my question here is do all of the VDD pins need to be routed to source power or are they internally connected enough for one or two of them to be enough? If they are, that would solve many a problem.
    ISTR Chip separated out a PLL Vdd, so you would need to be sure about power/filters on that one, but the others I would expect you could get away with decoupling-caps-only on the Core Vdd pins, with maybe 2 opposite-sides ones feeding power.

    Probably best established by doing a 4 layer PCB that does route every pin, and then doing a comparison with a cut-trace version to confirm.
    ie I'd start P2 testing on a more conservative PCB design, then see how much is actually needed, once that is proven....
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2017-10-02 02:43
    jmg wrote:
    I'd start P2 testing on a more conservative PCB design, then see how much is actually needed, once that is proven....
    But how do you prove it? IOW, how many use cases do you need to check before you can be certain that every use case can be accommodated by sparser power connections? IMO, Chip's pin assignments are a line in the sand that you don't peck away at, hoping to get by with something when there's really no sure way to determine if you can.

    We've been through this already with the P1: missing power connections and/or insufficient bypassing have led to PLL failures.

    I say, if you can't make all the connections and bypassing in two layers, you have no choice but to go to four.

    -Phil
  • evanhevanh Posts: 15,915
    Phil Pilgrim (PhiPi) wrote: »
    evanh wrote:
    My gut feeling is that's way more than needed and Chip was just filling in space.
    That's not an assumption that I'd be willing to make when laying out a board.
    threadz is happy to I believe.

    The big question is how many is he trying to do away with. I'm guessing he's wanting go below half.
  • threadzthreadz Posts: 56
    To be clear its not that I can't route all the traces in my design, its just that its really tedious and might mean giving up smoothing capacitors. Experience tells me to avoid that.
    Also, this seems like a problem most people will run into so if this issue can be addressed by changing the design it might be worth looking into while we have the chance.
    And by we I mean not me. This is out of my depth. I just want the magic black sand brick to do math good.

  • jmgjmg Posts: 15,173
    I did find this, but this may have been superseded...

    http://forums.parallax.com/discussion/comment/1393527/#Comment_1393527

    That suggests one VIO pin is used for the PLL_VDD filter, using a local follow-regulator and filtered Vdd_core feed.

    Looks like an up to date pinout is needed, for the PAD Ring that is in the FAB now, that shows PLL power dependent pins ?
  • jmgjmg Posts: 15,173
    threadz wrote: »
    To be clear its not that I can't route all the traces in my design, its just that its really tedious and might mean giving up smoothing capacitors. Experience tells me to avoid that.
    The best decoupling would be from caps underneath the Chip, on the PCB bottom.
    You could route using 0 ohm jumpers, which gives some trade off on layers-vs-BOM, and is also easy to remove/add for testing.

  • threadzthreadz Posts: 56
    jmg wrote: »
    The best decoupling would be from caps underneath the Chip, on the PCB bottom.

    that's the perfect fix to my problem. because of how the vias are set up there's nothing right under the chip itself. I'm kinda disappointed in myself for not seeing it sooner it's like right there.
    Weird question, is it possible to over-decouple? My gut says no but my gut also said other things that didn't go well
  • cgraceycgracey Posts: 14,152
    edited 2017-10-02 03:44
    ALL those VDD pins need to be connected. Same with the VIO's, of which there are so many, so that analog pin groups can be separately filtered. You don't want multiple LSBs of DAC drop on pins at the end of a power route on the chip. For that reason, each VIO pin feeds only two I/Os to the left and two I/Os to the right.

    I would put a VIO power ring on one side of the PCB, inside the pins, and a VDD ring directly on the other side. For the ring on the bottom, you would need vias to get to the pins on top.
  • jmgjmg Posts: 15,173
    threadz wrote: »
    Weird question, is it possible to over-decouple?
    Not really, but you should always check your regulator's stability rules (some few are only stable > some milliohm load ) and check your caps tolerance bands with bias.


    Some purists like to vary the decoupling caps, working on the theory that a smaller Cap has a higher series-resonant dip - I can believe that could matter in a RF design, but decoupling CMOS MCUs, I'm not sure that matters so much.
    If you leave one cap not fitted, you can probe the internal Core Vdd, and see how that compares with the decoupled Vdd pin-signals.


  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2017-10-02 04:01
    cgracey wrote:
    I would put a VIO power ring on one side of the PCB, inside the pins, and a VDD ring directly on the other side.
    Other side of the board, or other side of the pins? 'Trying to picture where the ground plane ends up ...

    -Phil
  • rjo__rjo__ Posts: 2,114
    threadz,

    Somewhere around here I saw a discussion. If I remember correctly, Parallax is planning to short circuit problems like this by producing a P2 module, to which I would add a smiley face and name it a "minion."
    (Kids will love it:)

    I would expect this early in the process.

    So, for low volumes, I think the design option to beat is doing it all yourself... and risking failure. OR design a board for your minion. Way more fun.



  • TubularTubular Posts: 4,702
    Chip, tell us what you're thinking with the ground pad under the P2. If its the same size as the die (~8.5mm^2) the space between it and the inside of the pins becomes useful for vias.

    If its much bigger than that, close to the pins, eg 14x14mm, it doesn't leave much room for internal vias.

    I've been using this strategy with the Max10, whose external pad is about 9x9mm

  • evanhevanh Posts: 15,915
    edited 2017-10-02 05:19
    cgracey wrote: »
    ALL those VDD pins need to be connected. Same with the VIO's, of which there are so many, so that analog pin groups can be separately filtered. You don't want multiple LSBs of DAC drop on pins at the end of a power route on the chip. For that reason, each VIO pin feeds only two I/Os to the left and two I/Os to the right.
    Chip,
    That doesn't really explain anything about VDD's needs.

    I find it hard to believe the Prop2 will be drawing more than 1 Amp for max rating of VDD. Even 8 pins is overkill for that. I'm guessing it's more likely 500 mA is what you're aiming for. If every second VDD is connected all the way round ...
  • cgraceycgracey Posts: 14,152
    Phil Pilgrim (PhiPi) wrote: »
    cgracey wrote:
    I would put a VIO power ring on one side of the PCB, inside the pins, and a VDD ring directly on the other side.
    Other side of the board, or other side of the pins? 'Trying to picture where the ground plane ends up ...

    -Phil

    I meant the other side of the board. Sorry.
  • cgraceycgracey Posts: 14,152
    Tubular wrote: »
    Chip, tell us what you're thinking with the ground pad under the P2. If its the same size as the die (~8.5mm^2) the space between it and the inside of the pins becomes useful for vias.

    If its much bigger than that, close to the pins, eg 14x14mm, it doesn't leave much room for internal vias.

    I've been using this strategy with the Max10, whose external pad is about 9x9mm

    Look at this and go to the 14 x 14 mm 100-lead exposed-pad package. You can see that the bond pad is 10.3 x 10.3 mm:

    https://www.amkor.com/go/packaging/all-packages/exposedpad-lqfp-/-tqfp/

    All the GND pads on the die are connected to that exposed pad.
  • cgraceycgracey Posts: 14,152
    evanh wrote: »
    cgracey wrote: »
    ALL those VDD pins need to be connected. Same with the VIO's, of which there are so many, so that analog pin groups can be separately filtered. You don't want multiple LSBs of DAC drop on pins at the end of a power route on the chip. For that reason, each VIO pin feeds only two I/Os to the left and two I/Os to the right.
    Chip,
    That doesn't really explain anything about VDD's needs.

    I find it hard to believe the Prop2 will be drawing more than 1 Amp for max rating of VDD. Even 8 pins is overkill for that. I'm guessing it's more likely 500 mA is what you're aiming for. If every second VDD is connected all the way round ...

    Without connecting all the VDD's, you will get local VDD drops on the internal power grid. I'm not sure how much current this thing will take. We'll know soon from the synthesis work.
  • ErNaErNa Posts: 1,752
    edited 2017-10-02 07:30
    Nowhere is more analog around than in a digital design! So the first to do is: have a sound basis. Voltages have to be clean, ground has to be ground.Slopes and and ringing contain much higher frequencies than clock. And every not perfect transition of a signal increases power losses. And: millions of billions (millions of millions of billions) transitions will occur, and not a single one is allowed to fail.
    So just follow proven engineering rules: do it right, do it right the first time and swamp the drains in a sea of c's. Clinton failed, Bush failed, and Obama failed. We won't fail if we follow Chips advice.
  • Heater.Heater. Posts: 21,230
    jmg,

    ErNa beat me to it. The only digital circuit designers are those that are designing RF circuits but don't know it :)

    One might have a digital signal toggling at 1Hz and think that is such a low frequency that not much care need be taken with it.

    But, the rise and fall times of such signals are very short. Those edges are well into the RF range. They can cause blips on the chips power supply. They can can cross talk into nearby signals.

    Ignoring the analog and high speed nature of digital circuits can lead to all kind of intermittent errors and head scratching. I first became painfully aware of this back in the 1980's when I was assigned the task of fixing "software glitches" on a multi-processor system. After much investigation I turned to the back plane buss that tied it all together. It was only operating at 1MHz and not very long but there was ringing and cross talk all over the place. Worked most of the time but.... Cleaning that mess up got everything working reliably.

    Chips have only gotten much faster since then!

    As for over decoupling. I guess it can be done. If all your decoupling caps are 1 Farad super caps the power supply will die when you turn it on. Or the traces melt !

    As for using different sizes and types of decoupling caps, we have to remember that a capacitor is not just a capacitor. It is also an inductor and resistor. All of which varies with frequency. Together with the impedance of your outputs, inductance and capacitance of your traces etc what we have is a horrible mess of analog circuitry, resonant circuits, etc. Most of which is still a black art to me...


  • evanhevanh Posts: 15,915
    edited 2017-10-02 10:57
    You can stop with the voodoo talk. Next, we'll be talking heath & safety at this rate.

  • threadzthreadz Posts: 56
    My take away here is:
    - Connect all the VDD and VIOs
    - Decouple with a few small SMD capacitors totaling a few microFarads.
    - No supercaps
    - No high speed or high current analog signals get near this IC because black magic
    - Pray
  • Heater.Heater. Posts: 21,230
    edited 2017-10-02 12:24
    By all means pray or summon up black magic. Whichever way your leanings go.

    However, just in case that does not work, it's best to employ sound engineering techniques. Even if one is not totally clear on the theory behind it. Then I'm sure the P2 will fly every time.

    Often companies produce reference designs for their chips. Including PCB layout around the pins, power distribution and decoupling where these things are critical. No doubt the first P2 boards from Parallax will show the way to go.
  • TonyB_TonyB_ Posts: 2,178
    Heater. wrote: »
    No doubt the first P2 boards from Parallax will show the way to go.

    Yes, when in doubt just copy what works.

    Monkey see, monkey do, monkey don't need to understand.

  • cgraceycgracey Posts: 14,152
    There are separate grounds on the die for VSS and GIO. They wind up common when bonded down to the exposed pad. This way, crazy digital noise on VSS doesn't destroy analog I/O integrity by polluting GIO via on-chip cross currents.
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