In our discussions with pjv, we realized that the Prop2 can be stripped down, pretty much exactly like we've been doing on various FPGA builds, and very significant savings can be realized in fabrication. And by using plain I/O's in place of some smart pins, the edge of the die can be shrunk greatly, while maintaining the same number of I/O's.
Smart pins take 330um, while plain I/O's can take only 100um. By making variants where groups of 4 pins alternate between smart and plain, the pad frame can be reduced dramatically. Then, the guts can be shrunk, as well, by reducing the cogs and the hub RAM.
To synthesize these variants, it's only a matter of parameters in my top-level Verilog module. Then, Treehouse must take our several existing pads, along with a new plain I/O, and assemble pad frames which accept the synthesized guts. Once we get everything scripted, with the constraints set for each type of pad, it becomes very easy (and inexpensive) to make variants.
OnSemi's cost for a 180nm mask set is about $60k, which is way less than I was thinking. I was adding in the initial production run cost, to make it more than that, in my head. Anyway, with simple-to-make layout variations and shuttle runs, we can make all these for a fraction of what we had assumed separate chips would cost.
We're on track for making the big one, first, but as soon as we prove that it works, we can start generating these other designs with little effort and moderate money.
Here's a set of pinouts for what seems like a well-divided family of parts. The smallest part will cost only ~20% of what the big one will. This way, you can prototype with the big guy and then target one that is sufficient. Note that each TQFP package size has two pin-compatible variants, allowing you to use a bigger or smaller part on the same PCB design, as long as your smart pins are in the same place where the lower version has its smart pins (as opposed to plain I/O's).
On second thought, that 28-pin version can have 4 cogs. Two is too few.