fastspin has x := if condition then eval_if_true else eval_if_false. This means adding one keyword, "then", but I think it's easier to read than C's version.
I think I like the C syntax better although maybe that's just because I'm used to it. Your syntax has too many identifiers in a row without any delimiters other than spaces to separate them. Although maybe that's because you've given a general case. This doesn't look quite so confusing:
This seems like a nice idea, although I'd probably swap the order of the count and array (that way there's no ambiguity about whether count is a user parameter or not -- anything after an array parameter is something inserted by the compiler.
I guess that depends upon which order the params end up on the stack. You want the count on top, I think, so you know how far down the param[] array extends.
Also, I like x := if a > 2 then a - 1 else a in lieu of a > 2 ? a - 1 : a.
It seems like there is a lot of discussion on the new Spin syntax, operator names and other things that have no impact on the silicon. I thought the sudden urgency of getting Spin working on the P2 was to uncover potential issues with the hardware design before it goes out to synthesis. Changing Spin syntax and operator names doesn't do a thing toward that goal, and in fact only delays the silicon even more. I was hoping for a merry Chipmas this year, but it seems more and more doubtful when I see all the random tweaks that are suggested for New Spin.
I tend to agree, but hopefully Chip is not taking too much notice of the higher level syntactic sugar diversions, and instead focuses on getting r16 images, and then byte-code engine tested on as many vehicles as possible - including XIP flows.
Tachyon is an obvious one.
I've been really looking forward to a ternary operator in Spin2. It makes code very compact in Verilog, especially when you have several of them.
Ideally, such a structure can also push all the way to code generation, and for smallest IF-ELSE choices, use a skip-style code generate. ie not jumps, but condition-code fall-thru.
Small skips will work much better with XIP code fetch, which has a relatively high cost attached to a jump, but less cost attached to skips, or serial code.
Interesting, Phil. That never occurred to me before.
I've been fighting Delphi most of the day. Turns out it blows up with 4k screen resolution. Had to back things down a bit.
The -A9 and -A7 compiles are all done now. It's strange that in the Cyclone V architecture, if utilization gets over ~93%, the compiler drags on for several hours and if it ever even finishes, the resulting Fmax is really poor.
Currently, I'm waiting for the DE2-115 compile to finish.
Interesting, Phil. That never occurred to me before.
I've been fighting Delphi most of the day. Turns out it blows up with 4k screen resolution. Had to back things down a bit.
The -A9 and -A7 compiles are all done now. It's strange that in the Cyclone V architecture, if utilization gets over ~93%, the compiler drags on for several hours and if it ever even finishes, the resulting Fmax is really poor.
Currently, I'm waiting for the DE2-115 compile to finish.
Fabulous!
Waiting for Quartus can be painful, especially when the final synth goes all weird.
Has there been any discussion of what to do with the ALTx and AUGx instructions? Will they appear on their own in source code or is the assembler expected to generate them automatically for new addressing modes? Has anyone come up with the syntax for those extended instructions? It seems like ALTx and AUGx?
Has there been any discussion of what to do with the ALTx and AUGx instructions? Will they appear on their own in source code or is the assembler expected to generate them automatically for new addressing modes? Has anyone come up with the syntax for those extended instructions?
Certainly where possible, the assembler should be able to generate them automatically, in which case they would appear in the LISTING file as 2 lines of ASM. ie managed in code flow, rather like any MACRO is.
Has there been any discussion of what to do with the ALTx and AUGx instructions? Will they appear on their own in source code or is the assembler expected to generate them automatically for new addressing modes? Has anyone come up with the syntax for those extended instructions? It seems like ALTx and AUGx?
ALTx is a prefix instruction and will always appear in source code.
AUGx is generated by Pnut when using immediate values with the ## option.
Only thing I see is that SETSE1/2/3/4 could move into one of the spare slots above which could allow the POLLINT..NIXINT3 to use SSSSSSSSS=000100000 which then affects the xxx/SETINT1/2/3and drops another line of spares at SSSSSSSSS=0001001ff.
Are all of the jump and branch instructions relative now? There are no absolute ones?
from the file "instructions_v15.txt"
For immediate-branch and LOC address operands, "#" is used before the
address. In cases where there is an option between absolute and relative
addressing, the assembler will choose absolute addressing when the branch
crosses between cog and hub domains, or relative addressing when the
branch stays in the same domain. Absolute addressing can be forced by
following "#" with "\".
Are all of the jump and branch instructions relative now? There are no absolute ones?
from the file "instructions_v15.txt"
For immediate-branch and LOC address operands, "#" is used before the
address. In cases where there is an option between absolute and relative
addressing, the assembler will choose absolute addressing when the branch
crosses between cog and hub domains, or relative addressing when the
branch stays in the same domain. Absolute addressing can be forced by
following "#" with "\".
Okay, I see. The absolute ones are in a different place in the instruction spreadsheet that I missed on my first glance. Sorry for the dumb question.
Why oh why do we need the horrible confusion of ternary expressions?
In fastspin's case I needed a ternary operator internally to implement some ranged bit expressions (things like outa[x..y] := z needed different handling depending on whether x < y). Since I had to implement it anyway it was trivial to expose it to the user. It's actually pretty common -- I think even Algol had it didn't it? (I'm sure Algol68 did, at least.)
Only thing I see is that SETSE1/2/3/4 could move into one of the spare slots above which could allow the POLLINT..NIXINT3 to use SSSSSSSSS=000100000 which then affects the xxx/SETINT1/2/3and drops another line of spares at SSSSSSSSS=0001001ff.
Probably not worth changing ???
The spare slots within CLKSET..QEXP are not worth using because that whole range is decoded as %00000xxxx, so that the 4 LSB's form hub commands. The other slot values get filled in with COGINIT..QVECTOR codes.
It would be neat to not use the D field for POLLINT..NIXINT3 and just use the S field, since there's plenty of space available. Wish I had done that. Would have kept things simpler and cleaner.
Only thing I see is that SETSE1/2/3/4 could move into one of the spare slots above which could allow the POLLINT..NIXINT3 to use SSSSSSSSS=000100000 which then affects the xxx/SETINT1/2/3and drops another line of spares at SSSSSSSSS=0001001ff.
Probably not worth changing ???
The spare slots within CLKSET..QEXP are not worth using because that whole range is decoded as %00000xxxx, so that the 4 LSB's form hub commands. The other slot values get filled in with COGINIT..QVECTOR codes.
That makes sense
It would be neat to not use the D field for POLLINT..NIXINT3 and just use the S field, since there's plenty of space available. Wish I had done that. Would have kept things simpler and cleaner.
Yes. Using S certainly contributed a lot of instruction expansion space when S wasn't required.
The instruction space is nice and tidy now. Did you see my latest post above where it breaks out the instruction space? eg see ROLBYTE
Did AUGS & AUGD need to be 2 clocks or was it just easier to keep it standard?
Why oh why do we need the horrible confusion of ternary expressions?
In fastspin's case I needed a ternary operator internally to implement some ranged bit expressions (things like outa[x..y] := z needed different handling depending on whether x < y). Since I had to implement it anyway it was trivial to expose it to the user. It's actually pretty common -- I think even Algol had it didn't it? (I'm sure Algol68 did, at least.)
I'm not opposed to ternary operators but can't help wondering how many ways we need to do the same thing, and how terse do we want to make them.
Why oh why do we need the horrible confusion of ternary expressions?
In fastspin's case I needed a ternary operator internally to implement some ranged bit expressions (things like outa[x..y] := z needed different handling depending on whether x < y). Since I had to implement it anyway it was trivial to expose it to the user. It's actually pretty common -- I think even Algol had it didn't it? (I'm sure Algol68 did, at least.)
I'm not opposed to ternary operators but can't help wondering how many ways we need to do the same thing, and how terse do we want to make them.
The advantage is that the ternary operator can be used in an expression. A regular if statement can't.
Comments
I think I like the C syntax better although maybe that's just because I'm used to it. Your syntax has too many identifiers in a row without any delimiters other than spaces to separate them. Although maybe that's because you've given a general case. This doesn't look quite so confusing:
Also, I like x := if a > 2 then a - 1 else a in lieu of a > 2 ? a - 1 : a.
-Phil
I've been really looking forward to a ternary operator in Spin2. It makes code very compact in Verilog, especially when you have several of them.
I tend to agree, but hopefully Chip is not taking too much notice of the higher level syntactic sugar diversions, and instead focuses on getting r16 images, and then byte-code engine tested on as many vehicles as possible - including XIP flows.
Tachyon is an obvious one.
Ideally, such a structure can also push all the way to code generation, and for smallest IF-ELSE choices, use a skip-style code generate. ie not jumps, but condition-code fall-thru.
Small skips will work much better with XIP code fetch, which has a relatively high cost attached to a jump, but less cost attached to skips, or serial code.
a := 50 if a < 5 else a * 10
a := 5 if a < 5
This puts the condition in the middle of the ternary operator and eliminates the then keyword.
-Phil
I've been fighting Delphi most of the day. Turns out it blows up with 4k screen resolution. Had to back things down a bit.
The -A9 and -A7 compiles are all done now. It's strange that in the Cyclone V architecture, if utilization gets over ~93%, the compiler drags on for several hours and if it ever even finishes, the resulting Fmax is really poor.
Currently, I'm waiting for the DE2-115 compile to finish.
Waiting for Quartus can be painful, especially when the final synth goes all weird.
Cond Opcode CZ I Dest Source Instr00 01 10 11 Operand(s) Flags ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 00000ff CZ I DDDDDDDDD SSSSSSSSS ROR ROL SHR SHL D,{#}S CZ CZ CZ CZ EEEE 00001ff CZ I DDDDDDDDD SSSSSSSSS RCR RCL SAR SAL D,{#}S CZ CZ CZ CZ EEEE 00010ff CZ I DDDDDDDDD SSSSSSSSS ADD ADDX ADDS ADDSX D,{#}S CZ CZ CZ CZ EEEE 00011ff CZ I DDDDDDDDD SSSSSSSSS SUB SUBX SUBS SUBSX D,{#}S CZ CZ CZ CZ EEEE 00100ff CZ I DDDDDDDDD SSSSSSSSS CMP CMPX CMPS CMPSX D,{#}S CZ CZ CZ CZ EEEE 00101ff CZ I DDDDDDDDD SSSSSSSSS CMPR CMPM SUBR CMPSUB D,{#}S CZ CZ CZ CZ EEEE 00110ff CZ I DDDDDDDDD SSSSSSSSS MIN MAX MINS MAXS D,{#}S CZ CZ CZ CZ EEEE 00111ff CZ I DDDDDDDDD SSSSSSSSS SUMC SUMNC SUMZ SUMNZ D,{#}S CZ CZ CZ CZ EEEE 01000ff CZ I DDDDDDDDD SSSSSSSSS BITL BITH BITC BITNC D,{#}S CZ CZ CZ CZ EEEE 01001ff CZ I DDDDDDDDD SSSSSSSSS BITZ BITNZ BITN BITX D,{#}S CZ CZ CZ CZ EEEE 01010ff CZ I DDDDDDDDD SSSSSSSSS ANDN AND OR XOR D,{#}S CZ CZ CZ CZ EEEE 01011ff CZ I DDDDDDDDD SSSSSSSSS MUXC MUXNC MUXZ MUXNZ D,{#}S CZ CZ CZ CZ EEEE 01100ff CZ I DDDDDDDDD SSSSSSSSS MOV NOT ABS NEG D,{#}S CZ CZ CZ CZ EEEE 01101ff CZ I DDDDDDDDD SSSSSSSSS NEGC NEGNC NEGZ NEGNZ D,{#}S CZ CZ CZ CZ EEEE 01110ff CZ I DDDDDDDDD SSSSSSSSS INCMOD DECMOD TOPONE BOTONE D,{#}S CZ CZ CZ CZ EEEE 01111ff CZ I DDDDDDDDD SSSSSSSSS TESTN TEST ANYB TESTB D,{#}S CZ CZ CZ CZ ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 1000ffN NN I DDDDDDDDD SSSSSSSSS SETNIB GETNIB ROLNIB www D,{#}S,#N (www)--+ -- -- -- EEEE 100011f NN I DDDDDDDDD SSSSSSSSS SETBYTE GETBYTE D,{#}S,#N <-----+ -- -- EEEE 1001000 NN I DDDDDDDDD SSSSSSSSS ROLBYTE xxx yyy zzz D,{#}S,#N (xxx)--+ (yyy)--+ (zzz)--+ -- EEEE 1001001 fn I DDDDDDDDD SSSSSSSSS SETWORD GETWORD D,{#}S,#N <-----+ | | -- -- EEEE 1001010 0N I DDDDDDDDD SSSSSSSSS ROLWORD vvv D,{#}S,#N (vvv)--+ \<----+ | -- EEEE 1001010 1f I DDDDDDDDD SSSSSSSSS ALTSN ALTGN D,{#}S <-----+ / | -- -- EEEE 1001011 ff I DDDDDDDDD SSSSSSSSS ALTSB ALTGB ALTSW ALTGW D,{#}S <-----+ -- -- -- -- EEEE 1001100 ff I DDDDDDDDD SSSSSSSSS ALTR ALTD ALTS ALTB D,{#}S -- -- -- -- EEEE 1001101 ff I DDDDDDDDD SSSSSSSSS ALTI SETR SETD SETS D,{#}S -- -- -- -- EEEE 1001110 ff I DDDDDDDDD SSSSSSSSS BMASK BMASKN TRIML TRIMR D,{#}S -- -- -- -- EEEE 1001111 ff I DDDDDDDDD SSSSSSSSS DECOD REV MOVBYTS SFUNC D,{#}S (SFUNC)--+ -- -- -- -- ----------------------------------------------------------------------------------------------------- | -------------------------------- EEEE 1001111 11 1 DDDDDDDDD 0000000ff SPLITB MERGEB SPLITW MERGEW D \<------+ -- -- -- -- EEEE 1001111 11 1 DDDDDDDDD 0000001ff SEUSSF SEUSSR RGBSQZ RGBEXP D / -- -- -- -- ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 101000f fZ I DDDDDDDDD SSSSSSSSS MUL MULS SCLU SCL D,{#}S -Z -Z -Z -Z EEEE 1010010 ff I DDDDDDDDD SSSSSSSSS ADDPIX MULPIX BLNPIX MIXPIX D,{#}S -- -- -- -- EEEE 1010011 ff I DDDDDDDDD SSSSSSSSS ADDCT1 ADDCT2 ADDCT3 WMLONG D,{#}S;D,{#}S;D,{#}S;D,{#}S/PTRx -- -- -- -- EEEE 1010100 Cf I DDDDDDDDD SSSSSSSSS RQPIN RDPIN D,{#}S C- C- EEEE 1010101 CZ I DDDDDDDDD SSSSSSSSS RDLUT D,{#}S CZ EEEE 101011f CZ I DDDDDDDDD SSSSSSSSS RDBYTE RDWORD D,{#}S/PTRx CZ CZ EEEE 101100f CZ I DDDDDDDDD SSSSSSSSS RDLONG CALLD D,{#}S/PTRx;D,{#}S CZ CZ EEEE 1011010 ff I DDDDDDDDD SSSSSSSSS IJZ IJNZ IJS IJNS D,{#}S -- -- -- -- EEEE 1011011 ff I DDDDDDDDD SSSSSSSSS DJZ DJNZ DJS DJNS D,{#}S -- -- -- -- EEEE 1011100 ff I DDDDDDDDD SSSSSSSSS TJZ TJNZ TJS TJNS D,{#}S -- -- -- -- EEEE 1011101 fL I DDDDDDDDD SSSSSSSSS JP JNP {#}D,{#}S -- -- EEEE 1011110 fL I DDDDDDDDD SSSSSSSSS CALLPA CALLPB {#}D,{#}S -- -- ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 1011111 01 I 0000000ff SSSSSSSSS JINT JCT1 JCT2 JCT3 {#}S -- -- -- -- EEEE 1011111 01 I 0000001ff SSSSSSSSS JSE1 JSE2 JSE3 JSE4 {#}S -- -- -- -- EEEE 1011111 01 I 0000010ff SSSSSSSSS JPAT JFBW JXMT JXFI {#}S -- -- -- -- EEEE 1011111 01 I 0000011ff SSSSSSSSS JXRO JXRL JATN JQMT {#}S -- -- -- -- EEEE 1011111 01 I 0000100ff SSSSSSSSS JNINT JNCT1 JNCT2 JNCT3 {#}S -- -- -- -- EEEE 1011111 01 I 0000101ff SSSSSSSSS JNSE1 JNSE2 JNSE3 JNSE4 {#}S -- -- -- -- EEEE 1011111 01 I 0000110ff SSSSSSSSS JNPAT JNFBW JNXMT JNXFI {#}S -- -- -- -- EEEE 1011111 01 I 0000111ff SSSSSSSSS JNXRO JNXRL JNATN JNQMT {#}S -- -- -- -- EEEE 1011111 1L I DDDDDDDDD SSSSSSSSS SETPAT {#}D,{#}S -- ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 110000f fL I DDDDDDDDD SSSSSSSSS WRPIN WXPIN WYPIN WRLUT {#}D,{#}S -- -- -- -- EEEE 110001f fL I DDDDDDDDD SSSSSSSSS WRBYTE WRWORD WRLONG RDFAST {#}D,{#}S/PTRx;{#}D,{#}S/PTRx;{#}D,{#}S/PTRx;{#}D,{#}S -- -- -- -- EEEE 110010f fL I DDDDDDDDD SSSSSSSSS WRFAST FBLOCK XINIT XZERO {#}D,{#}S -- -- -- -- EEEE 1100110 fL I DDDDDDDDD SSSSSSSSS XCONT REP {#}D,{#}S -- -- EEEE 1100111 CL I DDDDDDDDD SSSSSSSSS COGINIT {#}D,{#}S C- EEEE 110100f fL I DDDDDDDDD SSSSSSSSS QMUL QDIV QFRAC QSQRT {#}D,{#}S -- -- -- -- EEEE 1101010 fL I DDDDDDDDD SSSSSSSSS QROTATE QVECTOR {#}D,{#}S -- -- ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 1101011 C0 L DDDDDDDDD 0000000ff CLKSET COGID COGSTOP LOCKNEW {#}D;{#}D;{#}D;D C- C- -- C- EEEE 1101011 C0 0 DDDDDDDDD 0000001ff LOCKNEW LOCKRET LOCKCLR LOCKSET D;{#}D;{#}D;{#}D C- -- C- C- EEEE 1101011 CZ L DDDDDDDDD 0000010ff <spare> <spare> <spare> <spare> {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0000011ff <spare> <spare> <spare> <spare> {#}D CZ CZ CZ CZ EEEE 1101011 CZ 0 DDDDDDDDD 0000100ff RFBYTE RFWORD RFLONG WFBYTE D;D;D;{#}D CZ CZ CZ -- EEEE 1101011 00 L DDDDDDDDD 0000101ff WFWORD WFLONG SETQ SETQ2 {#}D -- -- -- -- EEEE 1101011 CZ 0 DDDDDDDDD 0000110ff GETQX GETQY GETCT GETRND D;D;D;{D} CZ CZ -- CZ EEEE 1101011 00 L DDDDDDDDD 0000111ff SETDACS SETXFRQ GETXCOS GETXSIN {#}D;{#}D;D;D -- -- -- -- EEEE 1101011 00 L DDDDDDDDD 0001000ff SETSE1 SETSE2 SETSE3 SETSE4 {#}D -- -- -- -- ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 1101011 C0 0 0000000ff 000100100 POLLINT POLLCT1 POLLCT2 POLLCT3 \ C- C- C- C- EEEE 1101011 C0 0 0000001ff 000100100 POLLSE1 POLLSE2 POLLSE3 POLLSE4 | C- C- C- C- EEEE 1101011 C0 0 0000010ff 000100100 POLLPAT POLLFBW POLLXMT POLLXFI | C- C- C- C- EEEE 1101011 C0 0 0000011ff 000100100 POLLXRO POLLXRL POLLATN POLLQMT | C- C- C- C- EEEE 1101011 C0 0 0000100ff 000100100 WAITINT WAITCT1 WAITCT2 WAITCT3 | C- C- C- C- EEEE 1101011 C0 0 0000101ff 000100100 WAITSE1 WAITSE2 WAITSE3 WAITSE4 |<-----+ C- C- C- C- EEEE 1101011 C0 0 0000110ff 000100100 WAITPAT WAITFBW WAITXMT WAITXFI | | C- C- C- C- EEEE 1101011 C0 0 0000111ff 000100100 WAITXRO WAITXRL WAITATN ALLOWI | | C- C- C- -- EEEE 1101011 00 0 0001000ff 000100100 ALLOWI STALLI TRGINT1 TRGINT2 | | -- -- -- -- EEEE 1101011 00 0 0001001ff 000100100 TRGINT3 NIXINT1 NIXINT2 NIXINT3 / | -- -- -- -- --------------------------------------------------------------------------------------------------- | ---------------------------------- EEEE 1101011 00 0 DDDDDDDDD 0001001ff xxx SETINT1 SETINT2 SETINT3 {#}D (xxx)--+ -- -- -- -- EEEE 1101011 00 L DDDDDDDDD 0001010ff WAITX SETCZ PUSH POP {#}D;{#}D;{#}D;D -- CZ -- CZ EEEE 1101011 CZ 0 DDDDDDDDD 0001011ff JMP CALL CALLA CALLB D CZ CZ CZ CZ EEEE 1101011 00 L DDDDDDDDD 0001100ff JMPREL RET RETA RETB {#}D;;; -- CZ CZ CZ EEEE 1101011 00 0 DDDDDDDDD 0001101ff GETPTR GETINT SETBRK SETLUT D;D;{#}D;{#}D -- -- -- -- EEEE 1101011 00 L DDDDDDDDD 0001110ff SETCY SETCI SETCQ SETCFRQ {#}D -- -- -- -- EEEE 1101011 00 L DDDDDDDDD 0001111ff SETCMOD SETPIX SETPIV COGATN {#}D -- -- -- -- EEEE 1101011 CZ L DDDDDDDDD 0010000ff DIRL DIRH DIRC DIRNC {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010001ff DIRZ DIRNZ DIRN TESTNIN {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010010ff OUTL OUTH OUTC OUTNC {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010011ff OUTZ OUTNZ OUTN TESTIN {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010100ff FLTL FLTH FLTC FLTNC {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010101ff FLTZ FLTNZ FLTN FLTRND {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010110ff DRVL DRVH DRVC DRVNC {#}D CZ CZ CZ CZ EEEE 1101011 CZ L DDDDDDDDD 0010111ff DRVZ DRVNZ DRVN DRVRND {#}D CZ CZ CZ CZ ---------------------------------------------------------------------------------------------------------------------------------------- EEEE 11011ff RA A AAAAAAAAA AAAAAAAAA JMP CALL CALLA CALLB #A -- -- -- -- EEEE 1110fWW RA A AAAAAAAAA AAAAAAAAA CALLD LOC PA/PB/PTRA/PTRB,#A -- -- EEEE 1111fNN NN N NNNNNNNNN NNNNNNNNN AUGS AUGD #N -- --AUGx is generated by Pnut when using immediate values with the ## option.
The instruction set decodes nice and clean.
Only thing I see is that SETSE1/2/3/4 could move into one of the spare slots above which could allow the POLLINT..NIXINT3 to use SSSSSSSSS=000100000 which then affects the xxx/SETINT1/2/3and drops another line of spares at SSSSSSSSS=0001001ff.
Probably not worth changing ???
I am not sure either if we really need them. It is just that they are pretty common lately.
But they just make sense in the common used form
exp ? true-part : false part.
if not in that common form its just another quirk with spin.
and stuff like
a := 50 if a < 5 else a * 10
a := 5 if a < 5
is not much shorter then
if a < 5 a := 50 else a *= 10
if a < 5 a := 5
just ugly
Mike
I think a single line if-else is worthwhile, but I'm less convinced a special new syntax is needed.
the alternative example above of
if a < 5 a := 50 else a *= 10
looks just fine to me. The then is implied, so no new keyword is required.
In fastspin's case I needed a ternary operator internally to implement some ranged bit expressions (things like outa[x..y] := z needed different handling depending on whether x < y). Since I had to implement it anyway it was trivial to expose it to the user. It's actually pretty common -- I think even Algol had it didn't it? (I'm sure Algol68 did, at least.)
The spare slots within CLKSET..QEXP are not worth using because that whole range is decoded as %00000xxxx, so that the 4 LSB's form hub commands. The other slot values get filled in with COGINIT..QVECTOR codes.
It would be neat to not use the D field for POLLINT..NIXINT3 and just use the S field, since there's plenty of space available. Wish I had done that. Would have kept things simpler and cleaner.
The instruction space is nice and tidy now. Did you see my latest post above where it breaks out the instruction space? eg see ROLBYTE
Did AUGS & AUGD need to be 2 clocks or was it just easier to keep it standard?
Is RDLUT 3 clocks for both cog-exec and lut-exec?
Is WRLUT 2 clocks for both cog-exec and lut-exec?
I'm not opposed to ternary operators but can't help wondering how many ways we need to do the same thing, and how terse do we want to make them.
Why can't we convert the current SPIN1and just use the existing bytecodes?
The inline assembly can be added next.
Then we can consider what needs changing/fixing/extending.
We don't want to really break the existing P1 spin code do we???
c := (a < 5 ? 5 : a) * 10
That's its primary utility, not just as a single-line if/else.
-Phil
Spin1 byte codes are limited to a 64k memory map.
That's right. It's awfully handy.