I got all the A7's back from the original customers that didn't want to keep them for $100. The whole point of that exercise was to not have to do any more A7 compiles for 50MHz.
So, now we have 16 new A9 boards that passed test, with 4 failed boards that can be repaired later. An A9 is needed to run all 16 cogs and 64 smart pins. Ken and I decided that we'll sell these for $400.
There's about a 0.5mm gap between the pcb and the underside of the fpga.
Based on a couple of trials I think the pre-tinned-with-solder, heated solid wire pushed in from the corner, has the best chance, and importantly can be pulled out again if it doesn't 'stick' to the joint
That sounds good too.
A little higher gauge, slightly flattened wire may get the heat in better, for that 'stick'
Are there 10 people here who'd take the A7 deal without that mod being done ?
Most people here could probably figure that out for themselves (OK, that's a guess!). I'm figuring someone will get a solution worked out and share.
Mainly the logic being that this can all happen much faster. No waiting for Chip to figure out a mod method, especially when that would delay P2 development time.
There are enough guys and gals here that can poke a wire into the P0 ball to make it work. Let's get them out of Parallax into the hands of the tinkerers.
At $200 a pop, that should be 2 grand to Parallax to help finish up P2.
Hmm. That was a bit toungue-in-cheek, but on reflection maybe not so mad.
I wonder if Chip would be willing to get the Sharpie out and autograph those 10? They are the first Parallax FPGA's. Something of a technology milestone.
This is good news to me cause I have an order in for the A9.
I was interested in A7, until I remembered the PLL issue.
It's a tough situation, I think, because you have a valuable product, with a major flaw.
I was thinking about those for P1V based emulation, but if that is also limited to 50 MHz, it's not so nice.
On the other hand, people buying with their own money can see an opportunity here.
Maybe it'd be nice if there was a third party who could repair the boards.
But, it would still add another board that Chip would have to support.
So, maybe a bondfire is best option. Probably illegal in CA though
It is a tough situation. The proposed price of the A 7 is great, but the reality of what 50MHz means re the P2 (Chip understandably not wanting to add a 50 MHz compliation) and the P1V, makes it a lot less desirable.
Don't want to interfere with Chip finalizing the P2, but if Parallax could hold off on the A 7 until after the design was done & then offer a fixed A7 at a slightly higher price, maybe that would work?? They would then be available to use for more folks to participate in the testing. On the other hand would there even be a benefit to Parallax of people testing / programming with the limited capability of the A7 P2 (number of cores & smart pins)?
I was interested in A7, until I remembered the PLL issue.
It's a tough situation, I think, because you have a valuable product, with a major flaw.
I was thinking about those for P1V based emulation, but if that is also limited to 50 MHz, it's not so nice.
Certainly they would need the repair, and based on what Tabular said, the fix sounds relatively simple, more a matter of scaling the wire up, until 'stick' is achieved. 0.5mm is reasonable access room.
Once one is done, the next 9 would be much faster.
Would providing an external clock serve the same purpose? It could be done as a modification to the Propeller loader program and have that Prop provide clock from a spare pin or else using one of the I2C controlled clocks (Silab chips?) again, controlled by the onboard Prop1 or as a completely external clock module.
I tried the ball one mod on my original A7 board and it never seemed to resolve the problem. Maybe it is trial and error or works for some boards but not others or there is more luck in getting the wire in the correct place.
The old A7 board still seems like heck of a deal for an FPGA development board at $200 and if it helps Parallax recover some (trivial) costs, all the better!
Here's a photo of what we did - involved removing a small patch of solder resist for a GND connection, then wedging the resistor in at a 45 degree angle so it hits pin 1
Here's a photo of what we did - involved removing a small patch of solder resist for a GND connection, then wedging the resistor in at a 45 degree angle so it hits pin 1
That looks nifty, can you probe a resistor corner, to verify connection ?
I think this is a current-mirror setup, so a connected R will have some Vdd-Vgs type voltage ?
We (OzPropDev and I, though he doesn't know it yet) have made an offer to Ken to fix up all the A7 boards, fixing then testing with OzPropDev's P1V test code that exercises pretty much everything on the board. We can replace any faulty ws2812b's, in addition to the precision resistor patch.
Due to our remote location, this'll add a week or two. By way of compensation we can throw in a 32 ch led test board we've been using with the A7 and A9.
We (OzPropDev and I, though he doesn't know it yet) have made an offer to Ken to fix up all the A7 boards, fixing then testing with OzPropDev's P1V test code that exercises pretty much everything on the board. We can replace any faulty ws2812b's, in addition to the precision resistor patch.
Due to our remote location, this'll add a week or two. By way of compensation we can throw in a 32 ch led test board we've been using with the A7 and A9.
Wouldn't this add $50-75 dollars (US) shipping to OZ then back to US?
We (OzPropDev and I, though he doesn't know it yet) have made an offer to Ken to fix up all the A7 boards, fixing then testing with OzPropDev's P1V test code that exercises pretty much everything on the board. We can replace any faulty ws2812b's, in addition to the precision resistor patch.
Due to our remote location, this'll add a week or two. By way of compensation we can throw in a 32 ch led test board we've been using with the A7 and A9.
No worries.
Anything we can do to assist with P2 development.
Happy to be involved.
I would be interested if I could use one already programmed as a P2 out of the box. I don't wish to have to buy a programmer and then also have to download some tools to my poor and limited Windows VM. Any possibility of that?
For the price, it is a really good offer. The board is a beauty, by the way.
I would be interested if I could use one already programmed as a P2 out of the box. I don't wish to have to buy a programmer and then also have to download some tools to my poor and limited Windows VM. Any possibility of that?
For the price, it is a really good offer. The board is a beauty, by the way.
It just uses a USB cable and a simple .exe program to load. No big install is necessary.
I would be interested if I could use one already programmed as a P2 out of the box. I don't wish to have to buy a programmer and then also have to download some tools to my poor and limited Windows VM. Any possibility of that?
For the price, it is a really good offer. The board is a beauty, by the way.
It just uses a USB cable and a simple .exe program to load. No big install is necessary.
Nice! If that is it, and if it performs like a P2, I can't wait.
I would be interested if I could use one already programmed as a P2 out of the box. I don't wish to have to buy a programmer and then also have to download some tools to my poor and limited Windows VM. Any possibility of that?
For the price, it is a really good offer. The board is a beauty, by the way.
We'll leave the test code installed and running on the A7's. The test code will either be running on top of a P1V, or a P2, depending on where Chip's images are at by then. That'll save using PX.EXE which might be an issue with other operating systems (but probably not)
Definitely I would be interested in having the FPGA loaded with the core for the P2, provided that we have a fully functional, 16 core equivalent. Is that the case? All 16 cores included?
As for the P1V, I'm not very interested, but I can always upgrade the board to the P2, so no issues there.
Comments
I got all the A7's back from the original customers that didn't want to keep them for $100. The whole point of that exercise was to not have to do any more A7 compiles for 50MHz.
So, now we have 16 new A9 boards that passed test, with 4 failed boards that can be repaired later. An A9 is needed to run all 16 cogs and 64 smart pins. Ken and I decided that we'll sell these for $400.
That sounds good too.
A little higher gauge, slightly flattened wire may get the heat in better, for that 'stick'
Good question, given the significant price difference, I would expect demand for fixed A7's - see above comment by Tubular.
We've got about 10 of them, I think. That's it.
Most people here could probably figure that out for themselves (OK, that's a guess!). I'm figuring someone will get a solution worked out and share.
Mainly the logic being that this can all happen much faster. No waiting for Chip to figure out a mod method, especially when that would delay P2 development time.
What's the sentiment?
At $200 a pop, that should be 2 grand to Parallax to help finish up P2.
The boards are so well made, they'd look just as good on the wall or in a glass case, as they would covered in cables and code on the workbench.
I wonder if Chip would be willing to get the Sharpie out and autograph those 10? They are the first Parallax FPGA's. Something of a technology milestone.
I was interested in A7, until I remembered the PLL issue.
It's a tough situation, I think, because you have a valuable product, with a major flaw.
I was thinking about those for P1V based emulation, but if that is also limited to 50 MHz, it's not so nice.
On the other hand, people buying with their own money can see an opportunity here.
Maybe it'd be nice if there was a third party who could repair the boards.
But, it would still add another board that Chip would have to support.
So, maybe a bondfire is best option. Probably illegal in CA though
Don't want to interfere with Chip finalizing the P2, but if Parallax could hold off on the A 7 until after the design was done & then offer a fixed A7 at a slightly higher price, maybe that would work?? They would then be available to use for more folks to participate in the testing. On the other hand would there even be a benefit to Parallax of people testing / programming with the limited capability of the A7 P2 (number of cores & smart pins)?
Tom
Once one is done, the next 9 would be much faster.
Where is Tabular located ?
Option 1: I'd fix them all to have one! (35 years experience with industrial board repair.)
Option 2: Bonfire is legal at my place...
I'll post some photos of what I did with a jammed in 0603 resistor, but I think the inserted wire might be better
I tried the ball one mod on my original A7 board and it never seemed to resolve the problem. Maybe it is trial and error or works for some boards but not others or there is more luck in getting the wire in the correct place.
The old A7 board still seems like heck of a deal for an FPGA development board at $200 and if it helps Parallax recover some (trivial) costs, all the better!
I think this is a current-mirror setup, so a connected R will have some Vdd-Vgs type voltage ?
In short you see smooth, purposeful color gradients when the connection is made, and sharp random transitions when it isn't.
We (OzPropDev and I, though he doesn't know it yet) have made an offer to Ken to fix up all the A7 boards, fixing then testing with OzPropDev's P1V test code that exercises pretty much everything on the board. We can replace any faulty ws2812b's, in addition to the precision resistor patch.
Due to our remote location, this'll add a week or two. By way of compensation we can throw in a 32 ch led test board we've been using with the A7 and A9.
Wouldn't this add $50-75 dollars (US) shipping to OZ then back to US?
Hehe, that's always the best kind of volunteer !!
same here
tom
No worries.
Anything we can do to assist with P2 development.
Happy to be involved.
For the price, it is a really good offer. The board is a beauty, by the way.
It just uses a USB cable and a simple .exe program to load. No big install is necessary.
Thanks, Chip.
We'll leave the test code installed and running on the A7's. The test code will either be running on top of a P1V, or a P2, depending on where Chip's images are at by then. That'll save using PX.EXE which might be an issue with other operating systems (but probably not)
Ken Gracey
As for the P1V, I'm not very interested, but I can always upgrade the board to the P2, so no issues there.
Kind regards, Samuel Lourenço