Parallax A-7 FPGA Boards - who's interested?
Ken Gracey
Posts: 7,386
in Propeller 2
Hey there,
We have 17 of these boards in stock that we could make available for sale. Our cost to build them (simply in Bill of Materials labor and parts) is about $350. Add in the design NRE and each one is probably worth more like $3,000!
Since we've moved on to the A-9 these boards are less desirable, obsolete for the P2 power developers. But they still have a nice loader, can run a Propeller 1 in entirety, and run half of a P2 design at 50 MHz. Specifically, 32 smart pins, 17 times.
Who would want one of these for $200? Support comes from the forums, Chip provides a P2 image, and schematic would be posted here too. Not the usual Parallax level of documentation and support you'd expect from our other products. No returns and all sales are final.
If there are enough people interested we'll make them available, make a P2 imagine, and launch another set of early adopters.
If you are interested, post your reply here stating so. If I see about ten people reply we'll post these for sale.
Thanks,
Ken Gracey
Parallax, Inc.
We have 17 of these boards in stock that we could make available for sale. Our cost to build them (simply in Bill of Materials labor and parts) is about $350. Add in the design NRE and each one is probably worth more like $3,000!
Since we've moved on to the A-9 these boards are less desirable, obsolete for the P2 power developers. But they still have a nice loader, can run a Propeller 1 in entirety, and run half of a P2 design at 50 MHz. Specifically, 32 smart pins, 17 times.
Who would want one of these for $200? Support comes from the forums, Chip provides a P2 image, and schematic would be posted here too. Not the usual Parallax level of documentation and support you'd expect from our other products. No returns and all sales are final.
If there are enough people interested we'll make them available, make a P2 imagine, and launch another set of early adopters.
If you are interested, post your reply here stating so. If I see about ten people reply we'll post these for sale.
Thanks,
Ken Gracey
Parallax, Inc.
Comments
I can only commit to one, but I'll take one more for Verilog learning and P1V hacking (plus they are just really built nicely)
Will the PLL resistor fix be installed? I would be interested in one.
I will purchase one.
Thanks,
Tom
I guess this means the P1V/P2 would only work at 50 MHz then.
I guess at $200, I will poke a wire to the pin to make it work.
It was handled in this thread.
http://forums.parallax.com/discussion/162130/pll-s-don-t-work-on-prop-1-2-3-fpga-a7-boards/p1
Circumstances won't allow me to buy an FPGA123-A9 for the time being, but I'm already ready for the P2 with my BeMicroCV-A9 I guess. An FPGA123-A7 would help me do some occasional partial P2 testing and would allow me to test the FPGA123 build from my own P1V Github repo.
===Jac
I'm leaving Parallax Rocklin at 2 pm on Tuesday and going straight to Chip's house. I will not leave Chip's house until we have tested the seventeen (17) A-7 boards and I have carefully packed them in a tidy box for transport back to Rocklin. Considering he will quickly become tired of my P2 requests (i.e., "just get it done already" and "pull out that USB stuff" etc.) and will do almost anything to make me stop I expect we'll get these boards tested and brought back to the mother ship by Wednesday.
If Wednesday comes and I'm still there I'll start feeding donuts and candy to his kids. This has a special way of changing the environment and atmosphere in the evening.
Ken Gracey
Will the testing process include fixing the ball one problem?
Thanks!
P.S. I will raise my payment by $10 to cover a couple big bags of M&M's if that helps!
Ken, we should look into making this fix, as it makes the board way more useful. I don't look forward to making special 50MHz-only compiles.
Based on a couple of trials I think the pre-tinned-with-solder, heated solid wire pushed in from the corner, has the best chance, and importantly can be pulled out again if it doesn't 'stick' to the joint
Remove the Oscillator, and connect the clock input of the FPGA to a free Prop1 pin. Then the Prop1 can generate a clock frequrncy with a counter PLL.
I don't know if the FPGA clk input is 3.3V compatible, otherwise a capacitive divider may help (or just a series cap).
Andy
Best do whatever is needed, for least-variation builds.
We're testing them now. You want photos?
Ken Gracey
It happens in my supply chain too! Sunday, I was talking with my daughter about ordering some multi-meter probes with micro-hooks on the ends.....yesterday, an envelope shows up from China with an assortment of multi-meter probes in it including the micro-hooks!
Being A9 boards, I'm guessing the price might be going up a bit?
More than a bit, and more than a byte, I reckon