Yep, 40MHz clock is there.
Here's my test code.
Runs fine at 20MHz, locks up at 40MHz.
I wonder if it has to do with the fact that the output is two clock cycles after a rising edge. In the case of 1-clock transitions (40MHz), the output of the current bit is on exactly the same edge as the detection for outputting the next bit.
Another thought about internal timing. When the output buffer becomes empty, Y is moved to the output buffer and INx is set, correct? For the output buffer, do you shift out the LSB to an interim FF on the clock edge, or is just shift it to the output FF two system clock cycles later? If the later is case, is there a possibility that the test for the getting the next bit is failing? After all, you would not yet have moved Y to the output buffer at the time of the next clock edge. (I'm not sure if I'm explaining this clearly.)
Yep, 40MHz clock is there.
Here's my test code.
Runs fine at 20MHz, locks up at 40MHz.
Did you try 40MHz Async ? - with a 40MHz continual FSCLK.
If you send 0xF0, as a first test, I think that will always echo something, no matter what FSCLK phase, but it may not always be stable.
That gets proof of concept, then phase can be looked at.
Manual Control of Clocked-Async Phase is possible, but in a Baud agnostic manner that quickly gets complex.
One solution, would be to allow a nearby pin, MUX access to the Async TxBaud clock.
That is always going to be stable in phase.
Comments
Another thought about internal timing. When the output buffer becomes empty, Y is moved to the output buffer and INx is set, correct? For the output buffer, do you shift out the LSB to an interim FF on the clock edge, or is just shift it to the output FF two system clock cycles later? If the later is case, is there a possibility that the test for the getting the next bit is failing? After all, you would not yet have moved Y to the output buffer at the time of the next clock edge. (I'm not sure if I'm explaining this clearly.)
Did you try 40MHz Async ? - with a 40MHz continual FSCLK.
If you send 0xF0, as a first test, I think that will always echo something, no matter what FSCLK phase, but it may not always be stable.
That gets proof of concept, then phase can be looked at.
Manual Control of Clocked-Async Phase is possible, but in a Baud agnostic manner that quickly gets complex.
One solution, would be to allow a nearby pin, MUX access to the Async TxBaud clock.
That is always going to be stable in phase.
Yes, @ozpropdev did. I can probably use that, but I was trying to do it how a new user might. See what's easy and what's not.
do you have a P1 ?
then have look here: SPLAT - the Propeller logic analyser you can run in an ansi terminal - poor man's logic analyser