The appeal of the P1 is that it's a simple, elegant, eminently useful, and strikingly beautiful design. One thing it is not, however, is scalable. It fits its boundaries precisely, like a cat squeezed into a cardboard box, with not a bit left over for expansion. I believe that it's this one aspect that is causing so much trouble in P2-land. People expect an enhanced Propeller in the P2, and it ain't gonna happen. It can't. Whatever the P2 becomes, it will not be a Propeller. And I think the point we've come to at the end of this latest development trajectory is evidence of that assertion.
Maybe the best thing we can do is stop calling it a P2. Perhaps "Q1" would be a better name for it. What made the P1 possible -- and successful -- is that Chip was starting from scratch with all new ideas. The idea that the P2 has somehow to reflect the P1's heritage is, it seems to me, entirely too constraining, like the bronchial contractions that lead to asthma. And again we find ourselves out of breath, waiting for some kind of super P1-spawn to emerge from the process. That might be asking too much.
Well, I trust Chip on this one. We've all been at this for quite some time, and a real chip needs to happen, and I know there is help in the right places on this one too. Chip has some personal visions for how he wants to see this go, and I'm in full support of those.
I very strongly agree with the documentation comments. This one has a lot of features and it just won't be necessary for people to jump in all the way to get a lot out of it. Later, when we are close, and we've got good tools running, etc... we can sort through this stuff, pluck out the ones that make great sense for newbies and document the Smile out of them, and leave code samples out there.
When that work gets done, this whole conversation will look a lot different.
Unless one is writing code on it every day, there is a lot happening! I am feeling that right now, having been away from a bit. Gonna just write some PASM tonight and get going. I suggest we all do the same and see how we feel about it all a coupla weeks from now.
It seems almost done at this core level. If so, we are on the home stretch to the smart pins!
I'm wondering if we really need these smart pins...
I think I'd vote for pushing the "print" button now...
(unless they're needed for USB that is...)
You cannot print something partially done.
Smart pins may include some USB low level support, but remember they must include the counters that are no longer in the COGs, and they include LCD mapping, and Serial Cells.
Good serial cells are going to be needed to talk to existing FLASH parts, up to QuadSPI and even DDR QuadSPI.
Then there is the evolution from that, of HyperBUS (Spansion) and the closely related XTRMFlash (Micron)
- that seems mainly an issue of getting test-situations.
Essentially, it appears to be Dual-QuadSPI with clock-closure.
Maybe the best thing we can do is stop calling it a P2. Perhaps "Q1" would be a better name for it. What made the P1 possible -- and successful -- is that Chip was starting from scratch with all new ideas. The idea that the P2 has somehow to reflect the P1's heritage is, it seems to me, entirely too constraining, like the bronchial contractions that lead to asthma.
I'd agree, it is far enough away from a P1 to need a well separated name. P2 confuses many into thinking it is closer to P1 than it really is.
That said, ST and SiLabs and Microchip do understand the importance of a family prefix.
ST have STM8/STM32, SiLabs have EFM8.EFM32 and Microchip have have PIC10.PIC12.PIC16.PIC18/PIC24/PIC32
I haven't bothered with the latest P2 incarnation for the following reasons:
* I don't have an FPGA board that will run a useful version of the P2
* The FPGA board I have *did* run a useful version of P2-hot and the instructions set seemed to be an extension of P1, this instruction set (from what I've seen) is not orthogonal to the P1 instructions, it's a whole new beast which takes brain cycles away from enjoyment
* Yeah, it's changing very fast, I just barely skim the forums any more because it is so difficult to follow
* You used to publish text docs of the instruction set in one place, I don't think I saw that (in a dedicated post) for the latest build
* The concepts of the P2_now are so dissimilar from the P1 that it barely resembles the P1. I liked how P2_hot was like a suped-up P1 in many ways
* I am somewhat unhappy with what looks like the decoupling of assets from each core, the P1 was a bunch of cores with duplicate assets, the P2_hot was similar. Now it seems much of the video stuff is decoupled from the cores, no waitvid to do the processing.
* Going back to an earlier post, the barrier to entry for testing is pretty high and leaves the testing to a select group of folks who spent a lot of money on resources
In comparison, some things I have been spending my mental and monetary resources on:
* I bought a Fadal VMC40 CNC machining center for cheap and I'm fixing it up
* I've been reverse engineering the early 80's control boards from the Fadal
* I've been disassembling the ROM code that runs the control
* I've been dreaming up ways to emulate the original ROM code on a newer processor
In comparison, the amount of time I have into the above is about double what I spent just writing the SHA-256 routine 3.5 years ago. It's been *that long* since I wrote that routine.
P2 seems to be dragging on, I'm just uncertain if there is a market at this juncture and if the sales of P2 will be sufficient to see a P3, pie in the sky chip, developed and released.
I'm also a bit disappointed at what the P2 takes away from what the P1 was capable of, interrupts are just an example of features that made it into P2 that were ghastly 3 years ago. The addressing scheme seems to be overly complex, I just don't understand why it can't be linear and why byte/long addressing is so different than P1.
The P2 had hardware threads that relied on the pipelining, but since you went to a 2 step instead of 4 step, it kinda eliminated that neat hack, now you've got interrupts doing time slicing. I'm not sure I'm happy with the complexity, the Intel and ARM chips can be quite complex, the P1's elegance was its simplicity, which was fast and made it enjoyable to program without a high level language obscuring the complexity.
I don't see how the P2_hot problem couldn't have been solved with a process change to 110nm, since it has 5x less leakage/dissipation than 180nm, it would have facilitated more memory too. Anyway, just my impressions.
* Yeah, it's changing very fast, I just barely skim the forums any more because it is so difficult to follow
* You used to publish text docs of the instruction set in one place, I don't think I saw that (in a dedicated post) for the latest build
All I can say is, I'm burnt out on this whole idea.
Seriously, why can't you just accept what you have now, lock it down, and move on to the smart-pins?
You've got the video generator in there again, and it's wonderfully adaptive as-is. STOP NOW.
Some comment was made about transparency. NO. STOP. STOP. STOP!
As an analogy: The COGS are done, don't overcook and over-spice it any further. Stop adding ingredients. Most of your dinner guests have already left the table and eaten at a crappy fast-food joint AND gotten over the heartburn/indigestion/guilt that entailed.
If you must resort to throwing out the complexity of smart pins due to writer's block, then just finish the necessary pin modes you already have designed (pullup, pulldown, open drain, differential pair, etc.), and build the chip!
Chip,
While I would have loved a P1+ (more hub ram, single cycle intructions, etc). I think that train has left the station.
Because of all the work put into the P2, I think it makes sense to complete it.
Your willingness to ask for input from the forum has resulted in a much better P2 design. But there comes a time when changes need to be stopped and the design fixed. Otherwise the changes will carry on forever. Yes, making a better chip, but one that will never be available.
I understand the drive to make something the best it can be. It's really hard to continue on with something after you find a better way that would make the design SO much better. It sucks, but it is neccessary.
I've said before "The P2 is going to be the greatest microcontroller never made." I really hope that is not the case, but how many years can you expect customers to wait ?
I'm really not trying to dump on Chip here. I'm just giving my honest opinion as a loyal customer of Parallax.
It's hard to get enthused about the P2 anymore, there's no timeline, the design isn't frozen, smart pins are well vaporware and no time line either.
At this rate it may never come to pass or when it does there may not be market for it. Really the P2 should have been rolled out several years ago. But it kept changing and growing and growing, then rewrites, etc.
If anything it shows the limitation of a one man design team. It doesn't work. Maybe Parallax has bitten off far more than they can chew trying to roll out a new microcontroller with limited resources.
Well, I have been scarce for quite a while... which is mostly due to non-propeller work, and having little to no free time.
I do plan on using P2 when it materializes, but for me, if hubexec is dropped, or the price is too high, I am unlikely to use the P2.
Even though I dusted off my DE2-115, I simply don't have time right now to play with the FPGA images, I hope to have some time next month.
I do try to visit at least once a week to catch up on the forum, and check out the latest documentation.
+ I love the larger CLUT, and clutexec
+ I like the interrupts and debugging
+ I love the streaming bandwidth, and I have a couple of ideas on how to improve hubexec quite a bit, but I'd get flamed on the forum, and I don't want to cause delays.
+ I like the new ALTS/D/I etc
The documentation, last time I looked on it, needs more explanation of interrupt handling, with samples (maybe I missed some).
- I really miss INDA/INDB
- The smart pins DESPERATELY need to be documented. How can I plan projects around the P2 without knowing exactly what they can do?
? One thing that is unclear to me is in the short constant branches, are the two LSB's wasted? If so, that is a huge mistake.
- I hate it when people keep asking for a 'reboot' of the design, or to cut hubexec. Seriously, this is begging to delay getting a chip out.
Frankly, I liked P2-Hot more, mostly because I could get significantly more performance out of it, and because hubexec ran about 50% faster on it. If not for the design reboot, we could be playing with real chips now. P2-Hot was more fun.
No more reboots, we need silicon.
There are multi-core Sitara A9's with 4x 200Mhz PRU's (think cogs).
I see that there's been a drop-off in activity over the last week here.
Are you guys finding that the Prop2 is not as fun as it could be?
Could it be that the chip is complex enough that you can't just go blazing into it like you could the Prop1? Or, maybe it's complex in unfriendly ways?
Could it be made simpler somehow, but still have lots of features? I know that complexity kills fun.
Is the lack of documentation the reason?
Are we getting bogged down in details? Does the chip's functionality seem ambiguous and not certain? Things have to feel solid to inspire confidence.
Maybe we need to rethink some basics.
I believe that if we had the right formula, people would be all over it, all the time. Maybe some formaldehyde seeped in. Maybe this whole egg-beater thing is giving people vertigo.
Yes, the cost of entry is high. FPGA images for the BeMicro-A9 could help with that but then since Chip would need to maintain another image for that, he probably needs some indication that would bring more testers into the pool.
Yes, it's a moving target but for the most part, it is becoming better and more refined and issues are being worked out as people actually write code for it and run code on it. (I thought that is why we are here).
Yes, the documentation is sparse but getting better. Guys, we got one resource to do it all. If it means I have to help bus tables or be a server, I'll help. I'd rather keep the Chef cooking that working on other things that may need to redone as things evolve.
Yes, the documentation is sparse but we're all smart cookies! Guys, it's *me* we're dealing with here, I haven't seriously programmed in assembler since 1991 and I've never really done much with PASM. I'm figuring it out, I'm making lights blink and stuff. I'm running in COG exec, HUB exec and LUT exec! You real engineers are more clever than I am, so jump in, it's not hard, really!!! I've proven that!
Hey, until you ask it to be something other than a P1, it's a more like a P1 than it's NOT like a P1!! Garb a cog and start coding! There are a few wrinkles but from bare metal, it is still A LOT easier to program (and more fun) than an ARM or a PIC32. (And it's still more fun!)
Tools??? Yes, tools will come, smart tools will come but now, let's keep it lean. PNUT needs to generate code so we can test. It doesn't need any bells and whistles and seriously, at this point, I don't think NOT being gas compatible is anything that any testers will notice. I don't think many testers come from a gas background or expect to be using gas right now to program a P2. All the things we find that would make an assembler better get noted down and built in OpenSpin2 or gas or PASM Royale for whatever it becomes. Unless it is a show stopper or is needed to generate test code, PNUT doesn't need to support it now.
A P1+?? Um, this *IS* the P1+! Remember like 18 months ago, we buried the P2-hot and came up with this as the start of the P1+? It might be a P1++++ by now but it's still a Propeller at its heart! It is as elegant and simple as it can be and offer the features it has.
You've come this far on the journey, are you really going to walk away now???? If this was easy, it wouldn't be as much fun!
I remember Ken saying that your designs tend to be very complex before you simplified them so take a break, enjoy the holidays, and start again refreshed next year.
I haven't read all replies to this so my apologies if this has already been said.
For me, personally, the primary reason why I rarely even browse anything P2 related is:
1) FPGA is still too hard for me. I only have a low-end FPGA board that cannot run the P2.
2) 99.9% of the reason I use P1 is for NTSC/VGA video. Especially NTSC. Which doesn't seem to be a huge focus for P2. Not that's a bad thing...
3) I just can't do anything with it because I don't have a good FPGA and I have no idea when the real chips will be available.
4) I will have to wait for cheap dev boards become available...which might not happen. I don't expect to see a through-hole version. :-D
However, I'm still excited to get my hands on one. I just know it won't be anytime soon. 2016 maybe? Not sure.
I found the P1 to actually be difficult to get into. I was never interested in Spin (no offense). Mainly because it is so proprietary. The assembly language piece, however, isn't bad at all. Mainly because there are only a few registers!
I also wonder how hobbyist friendly it will be. Especially for bread boarding.
Now, this is just me, but I would have been happy if the P2 was:
1) 8 cogs
2) 64 pins (lots of I/O for me)
3) 8k per COG
4) 512K HUB
5) Hardware SPI, I2C, etc. Shouldn't have to use a COG for 1-2 SPI or I2C devices.
6) 114.54544 MHz normal speed (32x NTSC colorburst)
7) NTSC/VGA should be even easier. Even if not backwards compatible.
8) 4 bit DAC on each COG
I think NTSC is now easier than P1. Chip just added it last week...
P1 video is a mysterious thing... P2 NTSC video output is still hidden a little, but Chip explained how it works.
But, usage is much simpler. I think this is because HUB RAM can now hold a whole screen buffer and the "streamer" does the heavy lifting...
So the P2 is going to have full NTSC support or is it just a way to create signals that could be used for NTSC?
It was a relatively late addition, but I would say NTSC has moved to the 'advanced' box.
ie not just a 'sort of' NTSC, but a more precise version that can be 'over-clocked'
Also see the other Color Space thread about ITU-R BT.656 - that has a 13.5MHz Luma dot clock, & 27MHz is a universal video chipset crystal
3) I just can't do anything with it because I don't have a good FPGA and I have no idea when the real chips will be available.
4) I will have to wait for cheap dev boards become available...which might not happen. I don't expect to see a through-hole version. :-D
You can do P2 testing & development with a more modest FPGA board, and there will be 0.1 " breakout modules available when the chip is real.
Once the final P2 image settles down*, there may even be possible a smaller 'standard module' that can have a P2 version and a FPGA version, to enable pre-silicon field deployment.
it is still undefined what size is needed for each of P2-COG+Cordic+SmartPins.
heater,
Where have you been?
Small NTSC Composite monitors are becoming more prevalent each day! Even some new model cars are beginning to have them inbuilt with a composite input. They are great for Prop projects that don't want a big VGA or HDMI monitor.
localroger:
A very informative post. Your details of how you use the P1 (ease of use) are precisely the way a number of us are using the P1 commercially. The ones I know about, mine included, are low volume and high priced items. In fact I use 3 props on one of my products. Each one of them could have been a cheaper alternative micro, or a combined single micro. But no other solution would be so easy to do.
You are of course correct, in that the P1 doesn't really do USB. It's my hope that the P2 will do USB FS by software. IMHO it doesn't necessarily need to be fully USB compliant, as long as it works reliably. I have done quite a bit of work getting P2 to do this but stopped when the P2 hot caused a major rethink. I will complete it once the P2 FPGA code becomes stable.
Sure there are alternative solutions to the USB aspect, such as the FTDI or similar for the USB to PC interface. Same goes for Keyboards with USB only - use USB Host chip(s). Same goes for converting/driving HDMI.
re P2:
It's now become quite obvious that the P2 aimed too high. We all thought that the P2 would be here long long ago. What we all really needed was a faster P1 with more hub RAM, more I/O, better/easier ADC, and preferably with security. There is a list of Parallax's customer requirements - I think there are 5 points on the list. All of these would be met with this faster P1.
I have to say, and I have said it before, IMHO it would be better to see the P2 be a faster P1 with those additions to meet those 5 points sooner, than the P2 which is just blowing out the timeline and costing a fortune. Just how long will the commercial P1 users who need the P2 (in some form) now wait before jumping ship.
I would also rather see if the boot Flash/Eeprom could be integrated in the new P2 (surely OnSemi have the technology to do this) and also an internal 1% oscillator (again lots of micros are doing this). These are the little things that would make an updated P1 great.
We have verified a few changes to the P1 by using the P1V, and the security was worked out long ago on the P2 together with a new boot monitor. The security would benefit from Flash/Eeprom, even if it was OTP.
All this would have less risk to Parallax than the now complex P2 which is going to require some extensive FPGA testing. And then there are going to be all the software tools which an updated P1 would not require. Coupled to this, Chip has learnt a few things to reduce power that could be implemented on an extended P1 design, such as using blocks of ram in the hub so that only part is selected each time the hub is accessed.
Meanwhile, I will just wait on the sidelines until something is announced.
Just for relevance, OnSemi make the CAT24C256 & CAT24C512 so they can make EEPROMs. I presume they must have purchased Catalyst.
Analog NTSC, PAL, VGA, Component aren't going anywhere any time soon.
The thing is they all are cheap and robust. And they don't require advanced processes and high clocks to use.
In the consumer space, there is clear pressure to go all digital. It's largely BOM cost and piracy driven. The BOM is always seeing those basics packaged in for less than the connector sub assembly. As for piracy... let's just say there be holes everywhere, not just analog.
Comments
Maybe the best thing we can do is stop calling it a P2. Perhaps "Q1" would be a better name for it. What made the P1 possible -- and successful -- is that Chip was starting from scratch with all new ideas. The idea that the P2 has somehow to reflect the P1's heritage is, it seems to me, entirely too constraining, like the bronchial contractions that lead to asthma. And again we find ourselves out of breath, waiting for some kind of super P1-spawn to emerge from the process. That might be asking too much.
-Phil
But, it's become a P1+++++++++++
I hope Chip leaves something for P3 and goes forward with this P2 in the near future...
Well, I trust Chip on this one. We've all been at this for quite some time, and a real chip needs to happen, and I know there is help in the right places on this one too. Chip has some personal visions for how he wants to see this go, and I'm in full support of those.
I very strongly agree with the documentation comments. This one has a lot of features and it just won't be necessary for people to jump in all the way to get a lot out of it. Later, when we are close, and we've got good tools running, etc... we can sort through this stuff, pluck out the ones that make great sense for newbies and document the Smile out of them, and leave code samples out there.
When that work gets done, this whole conversation will look a lot different.
Unless one is writing code on it every day, there is a lot happening! I am feeling that right now, having been away from a bit. Gonna just write some PASM tonight and get going. I suggest we all do the same and see how we feel about it all a coupla weeks from now.
It seems almost done at this core level. If so, we are on the home stretch to the smart pins!
Smart pins may include some USB low level support, but remember they must include the counters that are no longer in the COGs, and they include LCD mapping, and Serial Cells.
Good serial cells are going to be needed to talk to existing FLASH parts, up to QuadSPI and even DDR QuadSPI.
Then there is the evolution from that, of HyperBUS (Spansion) and the closely related XTRMFlash (Micron)
- that seems mainly an issue of getting test-situations.
Essentially, it appears to be Dual-QuadSPI with clock-closure.
?? - see above, you cannot 'skip' Smart Pins.
I'd agree, it is far enough away from a P1 to need a well separated name. P2 confuses many into thinking it is closer to P1 than it really is.
That said, ST and SiLabs and Microchip do understand the importance of a family prefix.
ST have STM8/STM32, SiLabs have EFM8.EFM32 and Microchip have have PIC10.PIC12.PIC16.PIC18/PIC24/PIC32
Does that mean a Prop16X512, or P16 for short ?
I haven't bothered with the latest P2 incarnation for the following reasons:
* I don't have an FPGA board that will run a useful version of the P2
* The FPGA board I have *did* run a useful version of P2-hot and the instructions set seemed to be an extension of P1, this instruction set (from what I've seen) is not orthogonal to the P1 instructions, it's a whole new beast which takes brain cycles away from enjoyment
* Yeah, it's changing very fast, I just barely skim the forums any more because it is so difficult to follow
* You used to publish text docs of the instruction set in one place, I don't think I saw that (in a dedicated post) for the latest build
* The concepts of the P2_now are so dissimilar from the P1 that it barely resembles the P1. I liked how P2_hot was like a suped-up P1 in many ways
* I am somewhat unhappy with what looks like the decoupling of assets from each core, the P1 was a bunch of cores with duplicate assets, the P2_hot was similar. Now it seems much of the video stuff is decoupled from the cores, no waitvid to do the processing.
* Going back to an earlier post, the barrier to entry for testing is pretty high and leaves the testing to a select group of folks who spent a lot of money on resources
In comparison, some things I have been spending my mental and monetary resources on:
* I bought a Fadal VMC40 CNC machining center for cheap and I'm fixing it up
* I've been reverse engineering the early 80's control boards from the Fadal
* I've been disassembling the ROM code that runs the control
* I've been dreaming up ways to emulate the original ROM code on a newer processor
In comparison, the amount of time I have into the above is about double what I spent just writing the SHA-256 routine 3.5 years ago. It's been *that long* since I wrote that routine.
P2 seems to be dragging on, I'm just uncertain if there is a market at this juncture and if the sales of P2 will be sufficient to see a P3, pie in the sky chip, developed and released.
I'm also a bit disappointed at what the P2 takes away from what the P1 was capable of, interrupts are just an example of features that made it into P2 that were ghastly 3 years ago. The addressing scheme seems to be overly complex, I just don't understand why it can't be linear and why byte/long addressing is so different than P1.
The P2 had hardware threads that relied on the pipelining, but since you went to a 2 step instead of 4 step, it kinda eliminated that neat hack, now you've got interrupts doing time slicing. I'm not sure I'm happy with the complexity, the Intel and ARM chips can be quite complex, the P1's elegance was its simplicity, which was fast and made it enjoyable to program without a high level language obscuring the complexity.
I don't see how the P2_hot problem couldn't have been solved with a process change to 110nm, since it has 5x less leakage/dissipation than 180nm, it would have facilitated more memory too. Anyway, just my impressions.
If you looked at this thread
http://forums.parallax.com/discussion/162298/prop2-fpga-files
you would find the GoogleDoc link in the first post
Seriously, why can't you just accept what you have now, lock it down, and move on to the smart-pins?
You've got the video generator in there again, and it's wonderfully adaptive as-is. STOP NOW.
Some comment was made about transparency. NO. STOP. STOP. STOP!
As an analogy: The COGS are done, don't overcook and over-spice it any further. Stop adding ingredients. Most of your dinner guests have already left the table and eaten at a crappy fast-food joint AND gotten over the heartburn/indigestion/guilt that entailed.
If you must resort to throwing out the complexity of smart pins due to writer's block, then just finish the necessary pin modes you already have designed (pullup, pulldown, open drain, differential pair, etc.), and build the chip!
While I would have loved a P1+ (more hub ram, single cycle intructions, etc). I think that train has left the station.
Because of all the work put into the P2, I think it makes sense to complete it.
Your willingness to ask for input from the forum has resulted in a much better P2 design. But there comes a time when changes need to be stopped and the design fixed. Otherwise the changes will carry on forever. Yes, making a better chip, but one that will never be available.
I understand the drive to make something the best it can be. It's really hard to continue on with something after you find a better way that would make the design SO much better. It sucks, but it is neccessary.
I've said before "The P2 is going to be the greatest microcontroller never made." I really hope that is not the case, but how many years can you expect customers to wait ?
I'm really not trying to dump on Chip here. I'm just giving my honest opinion as a loyal customer of Parallax.
Bean
Colourspace converter? NTSC output? Really? All for a few low volume sales.
How many years do I have to say that for?
At this rate it may never come to pass or when it does there may not be market for it. Really the P2 should have been rolled out several years ago. But it kept changing and growing and growing, then rewrites, etc.
If anything it shows the limitation of a one man design team. It doesn't work. Maybe Parallax has bitten off far more than they can chew trying to roll out a new microcontroller with limited resources.
I do plan on using P2 when it materializes, but for me, if hubexec is dropped, or the price is too high, I am unlikely to use the P2.
Even though I dusted off my DE2-115, I simply don't have time right now to play with the FPGA images, I hope to have some time next month.
I do try to visit at least once a week to catch up on the forum, and check out the latest documentation.
+ I love the larger CLUT, and clutexec
+ I like the interrupts and debugging
+ I love the streaming bandwidth, and I have a couple of ideas on how to improve hubexec quite a bit, but I'd get flamed on the forum, and I don't want to cause delays.
+ I like the new ALTS/D/I etc
The documentation, last time I looked on it, needs more explanation of interrupt handling, with samples (maybe I missed some).
- I really miss INDA/INDB
- The smart pins DESPERATELY need to be documented. How can I plan projects around the P2 without knowing exactly what they can do?
? One thing that is unclear to me is in the short constant branches, are the two LSB's wasted? If so, that is a huge mistake.
- I hate it when people keep asking for a 'reboot' of the design, or to cut hubexec. Seriously, this is begging to delay getting a chip out.
Frankly, I liked P2-Hot more, mostly because I could get significantly more performance out of it, and because hubexec ran about 50% faster on it. If not for the design reboot, we could be playing with real chips now. P2-Hot was more fun.
No more reboots, we need silicon.
There are multi-core Sitara A9's with 4x 200Mhz PRU's (think cogs).
Yes, the cost of entry is high. FPGA images for the BeMicro-A9 could help with that but then since Chip would need to maintain another image for that, he probably needs some indication that would bring more testers into the pool.
Yes, it's a moving target but for the most part, it is becoming better and more refined and issues are being worked out as people actually write code for it and run code on it. (I thought that is why we are here).
Yes, the documentation is sparse but getting better. Guys, we got one resource to do it all. If it means I have to help bus tables or be a server, I'll help. I'd rather keep the Chef cooking that working on other things that may need to redone as things evolve.
Yes, the documentation is sparse but we're all smart cookies! Guys, it's *me* we're dealing with here, I haven't seriously programmed in assembler since 1991 and I've never really done much with PASM. I'm figuring it out, I'm making lights blink and stuff. I'm running in COG exec, HUB exec and LUT exec! You real engineers are more clever than I am, so jump in, it's not hard, really!!! I've proven that!
Hey, until you ask it to be something other than a P1, it's a more like a P1 than it's NOT like a P1!! Garb a cog and start coding! There are a few wrinkles but from bare metal, it is still A LOT easier to program (and more fun) than an ARM or a PIC32. (And it's still more fun!)
Tools??? Yes, tools will come, smart tools will come but now, let's keep it lean. PNUT needs to generate code so we can test. It doesn't need any bells and whistles and seriously, at this point, I don't think NOT being gas compatible is anything that any testers will notice. I don't think many testers come from a gas background or expect to be using gas right now to program a P2. All the things we find that would make an assembler better get noted down and built in OpenSpin2 or gas or PASM Royale for whatever it becomes. Unless it is a show stopper or is needed to generate test code, PNUT doesn't need to support it now.
A P1+?? Um, this *IS* the P1+! Remember like 18 months ago, we buried the P2-hot and came up with this as the start of the P1+? It might be a P1++++ by now but it's still a Propeller at its heart! It is as elegant and simple as it can be and offer the features it has.
You've come this far on the journey, are you really going to walk away now???? If this was easy, it wouldn't be as much fun!
Well put mindrobots
I remember Ken saying that your designs tend to be very complex before you simplified them so take a break, enjoy the holidays, and start again refreshed next year.
There is always next Christmas
There is (if you look hard enough) and the latest milestone has already been missed.
For me, personally, the primary reason why I rarely even browse anything P2 related is:
1) FPGA is still too hard for me. I only have a low-end FPGA board that cannot run the P2.
2) 99.9% of the reason I use P1 is for NTSC/VGA video. Especially NTSC. Which doesn't seem to be a huge focus for P2. Not that's a bad thing...
3) I just can't do anything with it because I don't have a good FPGA and I have no idea when the real chips will be available.
4) I will have to wait for cheap dev boards become available...which might not happen. I don't expect to see a through-hole version. :-D
However, I'm still excited to get my hands on one. I just know it won't be anytime soon. 2016 maybe? Not sure.
I found the P1 to actually be difficult to get into. I was never interested in Spin (no offense). Mainly because it is so proprietary. The assembly language piece, however, isn't bad at all. Mainly because there are only a few registers!
I also wonder how hobbyist friendly it will be. Especially for bread boarding.
Now, this is just me, but I would have been happy if the P2 was:
1) 8 cogs
2) 64 pins (lots of I/O for me)
3) 8k per COG
4) 512K HUB
5) Hardware SPI, I2C, etc. Shouldn't have to use a COG for 1-2 SPI or I2C devices.
6) 114.54544 MHz normal speed (32x NTSC colorburst)
7) NTSC/VGA should be even easier. Even if not backwards compatible.
8) 4 bit DAC on each COG
:-)
P1 video is a mysterious thing... P2 NTSC video output is still hidden a little, but Chip explained how it works.
But, usage is much simpler. I think this is because HUB RAM can now hold a whole screen buffer and the "streamer" does the heavy lifting...
So the P2 is going to have full NTSC support or is it just a way to create signals that could be used for NTSC?
See the "color space converter" thread for details...
It was a relatively late addition, but I would say NTSC has moved to the 'advanced' box.
ie not just a 'sort of' NTSC, but a more precise version that can be 'over-clocked'
Also see the other Color Space thread about ITU-R BT.656 - that has a 13.5MHz Luma dot clock, & 27MHz is a universal video chipset crystal
You can do P2 testing & development with a more modest FPGA board, and there will be 0.1 " breakout modules available when the chip is real.
Once the final P2 image settles down*, there may even be possible a smaller 'standard module' that can have a P2 version and a FPGA version, to enable pre-silicon field deployment.
it is still undefined what size is needed for each of P2-COG+Cordic+SmartPins.
Where have you been?
Small NTSC Composite monitors are becoming more prevalent each day! Even some new model cars are beginning to have them inbuilt with a composite input. They are great for Prop projects that don't want a big VGA or HDMI monitor.
http://forums.parallax.com/discussion/comment/1329189/#Comment_1329189
Here is that post...
Just for relevance, OnSemi make the CAT24C256 & CAT24C512 so they can make EEPROMs. I presume they must have purchased Catalyst.
The thing is they all are cheap and robust. And they don't require advanced processes and high clocks to use.
In the consumer space, there is clear pressure to go all digital. It's largely BOM cost and piracy driven. The BOM is always seeing those basics packaged in for less than the connector sub assembly. As for piracy... let's just say there be holes everywhere, not just analog.