I haven't been as involved as I would like due to work commitments, but I have been following along with the forum when I have the time. Due to my limited time I'm waiting for things to solidify and be better documented before I dive in with the FPGA images. I do think moving forward is the only way to go, I don't think the project can survive another reboot.
The P2 is cool, really cool, but it is still just fantasy (as far as getting a real chip any time soon). While in the mean time a 64 I/O P1 with a more memory and a higher clock speed could have been done, and been part of real products, a long time ago. Every new feature concept, no matter how cool, just makes it feel like P2Hot is happening all over again.
The intellectual aspect of the P2 development is fun and educational to follow. Unfortunately in the mean time those of us who need more than a P1 are off looking at other chips to use instead of products from Parallax. Just look at what an assembled Arduino Due is capable of, for $15.00 including shipping...
My fear is that while Chip is having a blast with theoretical chip design Parallax is getting left further and further behind in sales. How long will it be before the revenue is not enough to continue to fund the eternal P2?
The P2 needs to be simple, cheap, flexible so someone can use it to come up with the next Pi or Arduino, or ??? that no one has thought of yet.
Parallax STARTED that whole concept with the Basic Stamp a long long time ago...
From the titbits I've read, the Prop1 can never be expanded verbatim. The original design files can no longer be used. The P1V files are not a perfect recreation, creating a Prop1+ from them would be only a similar chip.
It's not hard to see that Parallax decided to go straight to the Prop2 instead of trying to cobble together an approximation of the Prop1 plus extra bits.
I love the design. I've kind of been waiting for the next image, the A9... and sample code.
Every time I think I have figured out how to do something, an even better way seems to pop
up. The most recent idea that I like best (and really has nothing to do with the P2 design)` is the idea to have PNUT completely available from the command line. I've been looking around for a good host and keep returning to ImageJ, which can issue command line arguments and has serial lines and image processing.
I have it all running on a $99 tablet with 4 cameras under Windows 10.. just waiting for the A9 to take a self portrait:)
Personally I am waiting for Spin (preferably) or C. The only posts I have read about them are statements that things are too fluid to start work.
What concerns me is that I cannot see the finish line. On August 21st Chip wrote "We've got a date for final Verilog submission to Treehouse for synthesis: November 1st." Today is November 8 and features are still being added. Perhaps the forum category should be renamed Propeller Infinity.
Meanwhile improvements on Propeller 1 tools looks to have stalled.
IMHO, I believe the P2 should be suspended temporarily, and a new simpler specified P1+ should be made quickly. Something like...
P1 instruction set plus multiply and divide, and a relative jmpret
16 cogs with 4KB RAM (16KB in cog 0)
Hub 512KB RAM (or more)
64 I/O
Security fuses
Boot from SPI Flash
160-200MHz
Cog/hub access 1:16 32bit
Simple UART x2/4 in two cogs instead of VGA
No ADC???
That was sounding very similar to a P2, until you nobble it entirely, with this
No hubexec, but relative jmpret can use additional cog ram like Lutexec
It makes little sense to remove features that have been developed already, and a BIG device with no Hubexec would have a very small market.
What Parallax could do, is think about a same-die variant.
Other vendors do this, and they remove some testing costs,and get some yield coverage, and expand the market footprint with a family of parts, but they all come from the same die/wafers, and the same core design.
Yeah, the eggbeater brings speed, but uncertainty. Hub exec brings complexity. I think ambiguities surrounding addressing have taken a toll on people's enthusiasm.
This would be really fun and everyone could get into it:
A very simple 32-bit microcontroller that only has 16 logic, math, and branch instructions, but runs at 10,000 MIPS.
Everyone would grasp that in a minute and be off to the races. I would love something like that and it's dirt simple. It's just that technology doesn't quite allow it, yet.
It seems that when you want to make complicated things possible, you need lots of special hardware, which complicates the whole story.
I see that there's been a drop-off in activity over the last week here.
Are you guys finding that the Prop2 is not as fun as it could be?
Could it be that the chip is complex enough that you can't just go blazing into it like you could the Prop1? Or, maybe it's complex in unfriendly ways?
Could it be made simpler somehow, but still have lots of features? I know that complexity kills fun.
Is the lack of documentation the reason?
Are we getting bogged down in details? Does the chip's functionality seem ambiguous and not certain? Things have to feel solid to inspire confidence.
Maybe we need to rethink some basics.
I believe that if we had the right formula, people would be all over it, all the time. Maybe some formaldehyde seeped in. Maybe this whole egg-beater thing is giving people vertigo.
Do you have any notions about this?
Sadly I think the P2 has gone too far from the elegance and simplicity of P1, that in itself will make it harder for some people to grasp.
The one thing that drew me to Prop was how simply and quickly you could get something up and running.
That one 'feature' needs to remain no matter what.
For me there are too many 'features' that have been added, each one making the design more complex than the last.
Cluso99 has the right idea.
Chip, the P2 design needs to be fun to work with, it doesn't look like that from my perspective right now, I hope you manage to get there before ARM takes over the world (if they haven't already)
For me, following P2 development even peripherally would result in whiplash. Things are getting added and shuffled faster than I have the time or desire to pay attention to. (You lost me completely at interrupts.) One might even be forgiven for thinking that the P2 journey has become more captivating than the destination. So just a couple mantras to focus on:
Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint Exupéry
But also,
Perfect is the enemy of good. - Voltaire
IOW, keep it simple. Just wrap it up and get it done so Ken can start selling them -- and we can start buying them!
Conceptually the P2 is a much larger chip than the P1 and the "fun to work with" factor will depend much more on how the documentation is organized than the P1. Much like the P1's counters needed a whole application note with sample code, ObEx objects, etc., many of the P2's features will need whole chapters or separate documentation to show how to use them properly (and easily). You shouldn't have to learn about all of them to get started with Spin, basic I/O, PASM using essentially the P1 instructions. Having the C toolchain right up front will also help, particularly if the Propeller-specific library is the same.
For me there are too many 'features' that have been added, each one making the design more complex than the last.
That is true of pretty much all new MCUs :
For just over 30c, I can now buy a MCU with
* 12b ADC
* 5 Timers
* Calibrated Oscillators
* 256 Bytes RAM
* On Chip Debug
* UART/SPI/i2c
Do I expect to use all of those features at once ? Nope.
That part is cheap enough, it can sensibly replace even a couple of 555's or a 4060 and some gates, using just a small fraction of the available 'features'.
I worry less about "too many 'features'", or 'design complexity', as users can choose which they will use.
I do agree it is important for any single feature to be easy to use.
That comes from a combination of good silicon design, good docs, and good tool design.
I just want something quickly that solves the original commercial requirements. Ken posted a list years ago of about 4-5 requirements. IIRC my spec answers all these requirements. Note I said commercial!!! Hobbyists are not going to payback Parallax's investment!!!
That's why I said use the P1 (it is in Verilog as the P1V) and it works fine.
Don't bring in any of the P2 sections because they will take time or place risk in the project - only the couple I mentioned.
All existing tools will work as is without the extensions, and those few extensions will be easily added anyway. Plus no tools will take Chip's time!
This is why I said no hubexec because it requires too many changes.
I am certain Chip could do this all in a week (longer for us mortals). Hand it off to the ***tree*** guys to do their magic, and fingers crossed we could have final working silicon in a very short time.
Ken could get on with marketing and selling this, making lots of $$$ for Parallax.
Meanwhile Chip would be back onto the current P2 design (or whatever you want to call it).
And probably the break to a simpler design would "refresh" Chip too!
IMHO, without an interim solution, the P2 will be dead before it's out of the gate. We need something to keep the Propeller alive. Just IMHO.
Might be a good idea to update the first page (summary) of the P2 datasheet, to remind everyone including yourself what's being achieved. Having such a reference should pique the interest of newcomers too
We all really appreciate what you put into these projects. Your end products are a joy to use. That's why we're here any many others will join in as it becomes easier.
Time to lock things down and get ready to send it off? I'm sure that's not as much fun as the design phase, but there's a whole lot of fun waiting on the other side of that
I know how to simplify this P2 design a lot. At zero cost in time or money.
Do like Intel, Motorola and other famous names before. Leave all the unfinished or ill conceived instructions undocumented.
That way the simple folk, like me, don't get overloaded by a lot of confusing junk we probably don't need. Meanwhile the turbo users will find have great fun finding all the undocumented features, like they did back in the day.
I am certain Chip could do this all in a week (longer for us mortals). Hand it off to the ***tree*** guys to do their magic, and fingers crossed we could have final working silicon in a very short time.
Wow, a 1 week hand-over - I doubt anyone signing the cheques will consider that prudent.
That's why I said use the P1 (it is in Verilog as the P1V) and it works fine.
I can see the merit in working some more on P1V, but that does not have to involve Chip, or delay P2.
If your wish list is compelling enough, start a P1V fork with a view to possible chip design, and start code testing and tool testing.
Some have done this partially, but it is far from complete or 'silicon ready'.
You will need to prove all the pieces all work, before anyone will sign-off on silicon.
Same instruction set plus use the 4 free opcodes for
1. MUL
2. MULS
3. JMPREL (JMPRET but relative). The DJNZ etc will jump within the same currently executing 512-long cog page.
4. ??? DIV
16 Cogs, 64 I/O.
Cog RAM still single port, just extended to 4KB (1K-long) and hopefully Cog#0 with say 16KB.
Instructions still mostly 4 clocks (same as P1) but clock is at least 2x faster (160-200MHz).
Hub 512KB (or more), 2x faster so that cogs still get 1:16 access.
Boot from SPI Flash (not EEPROM).
Security bits and security boot.
ROM boot like P2.
Cogs 0..7 have video, and Cogs 8..15 have 1 or 2 simple serial units (not full uarts) - something like we use video as a serial out, but both directions.
This does not use the P1B hand design. It uses P1V as the base.
Yeah, the eggbeater brings speed, but uncertainty. Hub exec brings complexity. I think ambiguities surrounding addressing have taken a toll on people's enthusiasm.
This would be really fun and everyone could get into it:
A very simple 32-bit microcontroller that only has 16 logic, math, and branch instructions, but runs at 10,000 MIPS.
Everyone would grasp that in a minute and be off to the races. I would love something like that and it's dirt simple. It's just that technology doesn't quite allow it, yet.
It seems that when you want to make complicated things possible, you need lots of special hardware, which complicates the whole story.
Hey everybody 10,000 MIPS = 62 Propeller chips! or 133 SX chips....wew!! that is fast!!!!
This does not use the P1B hand design. It uses P1V as the base.
Understood.
(This fork probably needs its own thread.)
The choice of FPGA test vehicle is an interesting challenge, and there are a couple of ways to manage a P1V
* Use a large FPGA, and limit to Emulation only.
or
* Use a P1 and a smaller FPGA, for a co-processor approach, that has 8 P1 COGS + a smaller number of improved COGs
this would be cheap enough to make a Module.
or even both, with the co-processor module having field applications during and after design finalize.
For the smaller FPGA - QFN or BGA ?
The new Lattice iCE5LPxx (OTP+RAM) comes in 7mm QFN48 with 39 IO
Future show 50 @ $5.83 DK have then at $5.05
Altera MAX10 - 169-UBGA (11x11) or 153-MBGA (8x8) or 81-VBGA, WLCSP (4.5x4.4)
More logic, and $15-$25 at MAX10M08 size and $57 for MAX10M50, in 144-EQFP (20x20)
jmg,
I think you're misunderstanding what I am saying...
While I would love a P1+ yesterday, my reason for pushing for a P1+ is because I desperately believe that Parallax requires it for it's commercial customers NOW!!! I have been saying this for more than two years. And P2 is still not on the horizon. There is a lot of work still to be done such as the smart pins, and they have not even been started yet.
I don't have a commercial project in mind for a P1+, nor a P2. But there are plenty that do, although they are finding alternate solutions because they can no longer wait.
I have used 3 x P1's in a commercial project. It's not a high volume product. I don't intend to redesign it when P2 (or P1+) becomes available. So you see, I would rather use multiple P1's than a P1 with an FPGA, etc. BTW I have used FPGA's in commercial designs before. But they are not really replacements for the P1 or P2 market.
jmg,
I think you're misunderstanding what I am saying...
While I would love a P1+ yesterday, my reason for pushing for a P1+ is because I desperately believe that Parallax requires it for it's commercial customers NOW!!! I have been saying this for more than two years. And P2 is still not on the horizon.
Nor is a P1V+ - wishing for 'one week' developments, does not make it real. A lot of testing and proving is needed before a P1V+ can ever hope to move to silicon.
It is that important step, you seem to overlook, that I am focusing on.
...So you see, I would rather use multiple P1's than a P1 with an FPGA, etc. BTW I have used FPGA's in commercial designs before. But they are not really replacements for the P1 or P2 market.
That keeps changing with time.
I agree a large FPGA is not going to displace any MCU, but those small FPGA's do allow you to add incremental COGS of P1V+ to a design.
- and their price points continue to evolve.
Modules are commercial items today (just look at Bluetooth and wi-fi), plus all the modules Parallax sell now, and it is practical to have a P1+FPGA as a functioning module, that will fill a gap between P1 and P2.
I don't understand the push for a P1+ at this time when the P2 design is nearing completion. P1+ might have made sense when the P2Hot was abandoned, but I don't think it makes much sense now. And Cluso, you must be high on something if you think a P1+ design could be done in a week. It would take months to work out the design of a P1+ to the point where it could be handed over to Treehouse. All that is left for the P2 is to complete the SmartPins design and write up the ROM boot code. The key to completing the P2 design within the next few months relies on limiting the scope of SmartPins. If SmartPins is not well managed it could take years to complete it.
P1V is a working and verified Verilog code of the P1.
I have added Cog RAM and a few test instructions including AUGD/AUGS but I am not asking for them. Just the few Verilog lines.
Nothing extra here that Chip hasn't done before in short order. He's already crafted at least 3 versions - before the Thanksgiving rethink (was that 2 or 3 years ago???); the after Thanksgiving P2-Hot, and now the eggbeater.
If you think P2 is closer than a P1+ then you are dreaming.
I will raise the P1+ again in another 6 months time because there's no way we will have P2 silicon by then. From previous times quoted (I am just repeating as I have no idea) we could have P1+ silicon in less than 3 months, and that's virtually none of Chip's time. There's nothing complex to add to P1V. There is no marrying of the outer pin layout required to be done by Treehouse. All will be standard OnSemi cells.
IMHO Chip is over-tired and urgently needs a break. Get a P1+ out and then take a holiday. He'd come back afresh and perform another set of P2 miracles.
Rayman,
If we could push the print button now, I'd be arguing that. But the problems still in the current design makes me realise just how far away we are from adequate testing and debugging. And this is without the Smart Pins, which I think I agree, we should now skip.
A huge push was made for more memory. So we got more memory. Then, because of the big memory, we *must* have hubexec because anything less would be a waste of memory. Reminds me of our political system.
I would have loved a smaller faster cheaper Prop even it it were only 'sort of' like the P1. But P2 is what it is, and it surely ought to be finished asap. It will probably be vastly more useful and enjoyable than I imagine. But much depends on what 'smart pins' turn out to be (I have only the dimmest concept).
Meanwhile I'm spending almost all my programming time right now on the P1 which I still love dearly!
I think Chip once said that for (I forget the actual number) $60k, he could fabricate a digital only P2 chip. If this counts for where we are now, I think I'd just go for it...
It's a tiny user base right now, because it costs so much for fpga. If we could get 10,000 chips for $60k (again, I forget the actual numbers), they could push a $10 board with an actual P2, rev.A chip on it.
Ok, I found the post:
I requested commercial pricing from CMC for the 28nm process. I saw on CMP's site that you can get a 1.88 x 1.88 mm 28nm chip made for Euro 36,000, which isn't bad. That would have to be digital pins, only.
Doesn't say how many chips though... Maybe it's more like 1 than 10,000...
I think Beau said they got very luck on P1 to have it work, straight off. If I were loaded, I'd think $40k is a reasonable cost to check out the core logic...
Comments
Think the eggbeater is brilliant with fast reading.
But, I would like to see TV and VGA output working.
Also, I'd like to hear more about manufacturability...
C.W.
... wanting more specificity .... Inception, cool movie! Rayman, anything in particular?
I get nervous when Chip talks about adding in stuff from P2 hot
The intellectual aspect of the P2 development is fun and educational to follow. Unfortunately in the mean time those of us who need more than a P1 are off looking at other chips to use instead of products from Parallax. Just look at what an assembled Arduino Due is capable of, for $15.00 including shipping...
My fear is that while Chip is having a blast with theoretical chip design Parallax is getting left further and further behind in sales. How long will it be before the revenue is not enough to continue to fund the eternal P2?
The P2 needs to be simple, cheap, flexible so someone can use it to come up with the next Pi or Arduino, or ??? that no one has thought of yet.
Parallax STARTED that whole concept with the Basic Stamp a long long time ago...
It's not hard to see that Parallax decided to go straight to the Prop2 instead of trying to cobble together an approximation of the Prop1 plus extra bits.
Every time I think I have figured out how to do something, an even better way seems to pop
up. The most recent idea that I like best (and really has nothing to do with the P2 design)` is the idea to have PNUT completely available from the command line. I've been looking around for a good host and keep returning to ImageJ, which can issue command line arguments and has serial lines and image processing.
I have it all running on a $99 tablet with 4 cameras under Windows 10.. just waiting for the A9 to take a self portrait:)
What concerns me is that I cannot see the finish line. On August 21st Chip wrote "We've got a date for final Verilog submission to Treehouse for synthesis: November 1st." Today is November 8 and features are still being added. Perhaps the forum category should be renamed Propeller Infinity.
Meanwhile improvements on Propeller 1 tools looks to have stalled.
I am discouraged.
John Abshier
What Parallax could do, is think about a same-die variant.
Other vendors do this, and they remove some testing costs,and get some yield coverage, and expand the market footprint with a family of parts, but they all come from the same die/wafers, and the same core design.
Yes Chip go for it!!!!!!
Jeff
Sadly I think the P2 has gone too far from the elegance and simplicity of P1, that in itself will make it harder for some people to grasp.
The one thing that drew me to Prop was how simply and quickly you could get something up and running.
That one 'feature' needs to remain no matter what.
For me there are too many 'features' that have been added, each one making the design more complex than the last.
Cluso99 has the right idea.
Chip, the P2 design needs to be fun to work with, it doesn't look like that from my perspective right now, I hope you manage to get there before ARM takes over the world (if they haven't already)
But also,
IOW, keep it simple. Just wrap it up and get it done so Ken can start selling them -- and we can start buying them!
Cheers!
-Phil
That is true of pretty much all new MCUs :
For just over 30c, I can now buy a MCU with
* 12b ADC
* 5 Timers
* Calibrated Oscillators
* 256 Bytes RAM
* On Chip Debug
* UART/SPI/i2c
Do I expect to use all of those features at once ? Nope.
That part is cheap enough, it can sensibly replace even a couple of 555's or a 4060 and some gates, using just a small fraction of the available 'features'.
I worry less about "too many 'features'", or 'design complexity', as users can choose which they will use.
I do agree it is important for any single feature to be easy to use.
That comes from a combination of good silicon design, good docs, and good tool design.
I just want something quickly that solves the original commercial requirements. Ken posted a list years ago of about 4-5 requirements. IIRC my spec answers all these requirements.
Note I said commercial!!! Hobbyists are not going to payback Parallax's investment!!!
That's why I said use the P1 (it is in Verilog as the P1V) and it works fine.
Don't bring in any of the P2 sections because they will take time or place risk in the project - only the couple I mentioned.
All existing tools will work as is without the extensions, and those few extensions will be easily added anyway. Plus no tools will take Chip's time!
This is why I said no hubexec because it requires too many changes.
I am certain Chip could do this all in a week (longer for us mortals). Hand it off to the ***tree*** guys to do their magic, and fingers crossed we could have final working silicon in a very short time.
Ken could get on with marketing and selling this, making lots of $$$ for Parallax.
Meanwhile Chip would be back onto the current P2 design (or whatever you want to call it).
And probably the break to a simpler design would "refresh" Chip too!
IMHO, without an interim solution, the P2 will be dead before it's out of the gate. We need something to keep the Propeller alive. Just IMHO.
Might be a good idea to update the first page (summary) of the P2 datasheet, to remind everyone including yourself what's being achieved. Having such a reference should pique the interest of newcomers too
We all really appreciate what you put into these projects. Your end products are a joy to use. That's why we're here any many others will join in as it becomes easier.
Time to lock things down and get ready to send it off? I'm sure that's not as much fun as the design phase, but there's a whole lot of fun waiting on the other side of that
Let us know if we can help.
regards
Lachlan
Do like Intel, Motorola and other famous names before. Leave all the unfinished or ill conceived instructions undocumented.
That way the simple folk, like me, don't get overloaded by a lot of confusing junk we probably don't need. Meanwhile the turbo users will find have great fun finding all the undocumented features, like they did back in the day.
Wow, a 1 week hand-over - I doubt anyone signing the cheques will consider that prudent.
I can see the merit in working some more on P1V, but that does not have to involve Chip, or delay P2.
If your wish list is compelling enough, start a P1V fork with a view to possible chip design, and start code testing and tool testing.
Some have done this partially, but it is far from complete or 'silicon ready'.
You will need to prove all the pieces all work, before anyone will sign-off on silicon.
Same instruction set plus use the 4 free opcodes for
1. MUL
2. MULS
3. JMPREL (JMPRET but relative). The DJNZ etc will jump within the same currently executing 512-long cog page.
4. ??? DIV
16 Cogs, 64 I/O.
Cog RAM still single port, just extended to 4KB (1K-long) and hopefully Cog#0 with say 16KB.
Instructions still mostly 4 clocks (same as P1) but clock is at least 2x faster (160-200MHz).
Hub 512KB (or more), 2x faster so that cogs still get 1:16 access.
Boot from SPI Flash (not EEPROM).
Security bits and security boot.
ROM boot like P2.
Cogs 0..7 have video, and Cogs 8..15 have 1 or 2 simple serial units (not full uarts) - something like we use video as a serial out, but both directions.
This does not use the P1B hand design. It uses P1V as the base.
Hey everybody 10,000 MIPS = 62 Propeller chips! or 133 SX chips....wew!! that is fast!!!!
Jeff
Understood.
(This fork probably needs its own thread.)
The choice of FPGA test vehicle is an interesting challenge, and there are a couple of ways to manage a P1V
* Use a large FPGA, and limit to Emulation only.
or
* Use a P1 and a smaller FPGA, for a co-processor approach, that has 8 P1 COGS + a smaller number of improved COGs
this would be cheap enough to make a Module.
or even both, with the co-processor module having field applications during and after design finalize.
For the smaller FPGA - QFN or BGA ?
The new Lattice iCE5LPxx (OTP+RAM) comes in 7mm QFN48 with 39 IO
Future show 50 @ $5.83 DK have then at $5.05
Altera MAX10 - 169-UBGA (11x11) or 153-MBGA (8x8) or 81-VBGA, WLCSP (4.5x4.4)
More logic, and $15-$25 at MAX10M08 size and $57 for MAX10M50, in 144-EQFP (20x20)
I think you're misunderstanding what I am saying...
While I would love a P1+ yesterday, my reason for pushing for a P1+ is because I desperately believe that Parallax requires it for it's commercial customers NOW!!! I have been saying this for more than two years. And P2 is still not on the horizon. There is a lot of work still to be done such as the smart pins, and they have not even been started yet.
I don't have a commercial project in mind for a P1+, nor a P2. But there are plenty that do, although they are finding alternate solutions because they can no longer wait.
I have used 3 x P1's in a commercial project. It's not a high volume product. I don't intend to redesign it when P2 (or P1+) becomes available. So you see, I would rather use multiple P1's than a P1 with an FPGA, etc. BTW I have used FPGA's in commercial designs before. But they are not really replacements for the P1 or P2 market.
Nor is a P1V+ - wishing for 'one week' developments, does not make it real.
A lot of testing and proving is needed before a P1V+ can ever hope to move to silicon.
It is that important step, you seem to overlook, that I am focusing on.
That keeps changing with time.
I agree a large FPGA is not going to displace any MCU, but those small FPGA's do allow you to add incremental COGS of P1V+ to a design.
- and their price points continue to evolve.
Modules are commercial items today (just look at Bluetooth and wi-fi), plus all the modules Parallax sell now, and it is practical to have a P1+FPGA as a functioning module, that will fill a gap between P1 and P2.
I think I'd vote for pushing the "print" button now...
(unless they're needed for USB that is...)
I have added Cog RAM and a few test instructions including AUGD/AUGS but I am not asking for them. Just the few Verilog lines.
Nothing extra here that Chip hasn't done before in short order. He's already crafted at least 3 versions - before the Thanksgiving rethink (was that 2 or 3 years ago???); the after Thanksgiving P2-Hot, and now the eggbeater.
If you think P2 is closer than a P1+ then you are dreaming.
I will raise the P1+ again in another 6 months time because there's no way we will have P2 silicon by then. From previous times quoted (I am just repeating as I have no idea) we could have P1+ silicon in less than 3 months, and that's virtually none of Chip's time. There's nothing complex to add to P1V. There is no marrying of the outer pin layout required to be done by Treehouse. All will be standard OnSemi cells.
IMHO Chip is over-tired and urgently needs a break. Get a P1+ out and then take a holiday. He'd come back afresh and perform another set of P2 miracles.
Rayman,
If we could push the print button now, I'd be arguing that. But the problems still in the current design makes me realise just how far away we are from adequate testing and debugging. And this is without the Smart Pins, which I think I agree, we should now skip.
Enough said.
I would have loved a smaller faster cheaper Prop even it it were only 'sort of' like the P1. But P2 is what it is, and it surely ought to be finished asap. It will probably be vastly more useful and enjoyable than I imagine. But much depends on what 'smart pins' turn out to be (I have only the dimmest concept).
Meanwhile I'm spending almost all my programming time right now on the P1 which I still love dearly!
It's a tiny user base right now, because it costs so much for fpga. If we could get 10,000 chips for $60k (again, I forget the actual numbers), they could push a $10 board with an actual P2, rev.A chip on it.
Ok, I found the post:
I requested commercial pricing from CMC for the 28nm process. I saw on CMP's site that you can get a 1.88 x 1.88 mm 28nm chip made for Euro 36,000, which isn't bad. That would have to be digital pins, only.
Doesn't say how many chips though... Maybe it's more like 1 than 10,000...
I think Beau said they got very luck on P1 to have it work, straight off. If I were loaded, I'd think $40k is a reasonable cost to check out the core logic...