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Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i - Page 25 — Parallax Forums

Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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  • Cluso99Cluso99 Posts: 18,069
    Chip,
    Can the streamer work both ways? (ie can you stream input?)
    Without knowing precisely how it is working, and if you can bypass the DACs, could it be used to stream bits in and out for high speed serial?
  • cgraceycgracey Posts: 14,209
    Cluso99 wrote: »
    Chip,
    Can the streamer work both ways? (ie can you stream input?)
    Without knowing precisely how it is working, and if you can bypass the DACs, could it be used to stream bits in and out for high speed serial?

    Sure, but it works on bytes, words, and longs, not bits. It might be a simple matter to make it do bits, though.
  • jmgjmg Posts: 15,175
    cgracey wrote: »
    Cluso99 wrote: »
    ... could it be used to stream bits in and out for high speed serial?

    Sure, but it works on bytes, words, and longs, not bits. It might be a simple matter to make it do bits, though.

    How is that different from this discussion below ? ie is 1 bit video not doing bits ?
    cgracey wrote:
    Rayman wrote:
    Excellent. BTW: I don't know how easy it would be but, 1,2, and 4 bit streaming options might be nice for high resolution text and simple graphic outputs...

    It's all in there, already.
  • cgraceycgracey Posts: 14,209
    jmg wrote: »
    cgracey wrote: »
    Cluso99 wrote: »
    ... could it be used to stream bits in and out for high speed serial?

    Sure, but it works on bytes, words, and longs, not bits. It might be a simple matter to make it do bits, though.

    How is that different from this discussion below ? ie is 1 bit video not doing bits ?
    cgracey wrote:
    Rayman wrote:
    Excellent. BTW: I don't know how easy it would be but, 1,2, and 4 bit streaming options might be nice for high resolution text and simple graphic outputs...

    It's all in there, already.

    Ah, you're right. There is a 1-bit LUT mode. Inputting is the problem.
  • RaymanRayman Posts: 14,768
    Streaming input and output aren't symmetric anyway, right?

    Output goes via DACs to 1 to 4 pins, inputs come from sets of I/O pins.(?)
  • cgraceycgracey Posts: 14,209
    Rayman wrote: »
    Streaming input and output aren't symmetric anyway, right?

    Output goes via DACs to 1 to 4 pins, inputs come from sets of I/O pins.(?)

    You can output the raw binary to pins, if you want.

    Our streaming in is only bytes, words, or longs.
  • jmgjmg Posts: 15,175
    edited 2015-11-10 23:22
    So table is like :

    Streaming OUT
    1,2,4,8,16,32 bit streaming
    Can drive 1,2,3,4 (?) DACS, or feed direct to 1,2,4,8,16,32 wide parallel pins
    Clock generated ? or CLK input ?

    Streaming IN
    Currently 8,16,32 bit streaming, from Pins
    (also from ADC ?)
    Clock generated ? or CLK input ?

    Some of this overlaps with smart pins, but if the streamer can output certain formats, there is an easy to follow symmetry about being able to input the same formats - even if it just allows simpler testing.
  • RaymanRayman Posts: 14,768
    pixel clock output would be great then...
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2015-11-10 23:34
    Chip, how about a link in your top post and/or in your document to the assembly instruction set document we have been building. I've been going over every instruction and giving it its own entry with color-coded bitfields. As you know the master document can be edited also (hint hint). Cheers

    P.S. I find the color-coding gives me a quick picture of the type of instruction it is.
  • Dave HeinDave Hein Posts: 6,347
    I'm trying to track down the specification for the ALTI (formerly ALTDS) instruction. Does this post from September 14 describe the instruction correctly? http://forums.parallax.com/discussion/comment/1344546/#Comment_1344546
  • User NameUser Name Posts: 1,451
    edited 2015-11-11 02:10
    Peter Jakacki wrote: »
    Chip, how about a link in your top post and/or in your document to the assembly instruction set document we have been building.

    Wow, I didn't know so much documentation existed! Both the document Peter links here and the link to "Chip's document" are great. I wonder if I'm the only dimwit who didn't realize until now that there was already a critical mass of information assembled and readily accessible.

    Also, it has been a while since I read any sort of summary of what the Turbine2 contains. After reading Chip's description of the new device, I'm stunned and amazed!

  • mindrobotsmindrobots Posts: 6,506
    Wait until you take it for a test drive! It's really cool!
  • Cluso99Cluso99 Posts: 18,069
    Chip,
    If easy, it would be nice to be able to stream bits in from an input pin.
    It might be better for me/us to understand the whole streaming part first.
  • cgraceycgracey Posts: 14,209
    Cluso99 wrote: »
    Chip,
    If easy, it would be nice to be able to stream bits in from an input pin.
    It might be better for me/us to understand the whole streaming part first.

    I'm documenting the streamer right now.
  • cgraceycgracey Posts: 14,209
    I got the streamer documented. It doesn't have any examples, but I think you guys can understand the modes enough to use them.
  • BaggersBaggers Posts: 3,019
    Nice one Chip, will have a play later this evening when I get home, probably 10pm with it being crunch time ( Friday release )
  • RaymanRayman Posts: 14,768
    edited 2015-11-11 12:12
    Lots of modes to digest there...

    Saw mention on ADCs. Wasn't sure they were still in the plans...

    Don't immediately see how you can do hsync and vsync for VGA, but I'm sure you have plan...
  • TharkunTharkun Posts: 67
    cgracey wrote: »
    Tharkun wrote: »
    Hi,

    last week i bought a DE0-Nano on ebay (for a good price:)
    I play around with it and do some programming examples, it all works.

    For the first prop2 test i used the "DE0_Nano_Bare_Prop2_v3.jic" with USB-Serial-Prog like shown
    in "DE0_Nano_Bare_Prop2_Hookup" - no problems.

    Now i would like to use my self made DAC:

    DE0_DAC.jpg

    Do i have to use the "DE0_Nano_Prop2_v3.jic" image ?
    PNut finds no more Propeller 2 with this image or do i have to use other Prog-Pins ?
    I also try out GPIO_211/212/0 _IN_0 instead of GPIO_3/5/7.
    I'm a little bit confused. What is the exact difference between those both Nano-Images ?

    Thanks in advance

    Tharkun,

    Here is the pinout list that maps the DE0_Nano's FPGA pins to the DACs and everything:
    set_location_assignment PIN_D3 -to io[0] (P0..)
set_location_assignment PIN_C3 -to io[1]
set_location_assignment PIN_A2 -to io[2]
set_location_assignment PIN_A3 -to io[3]
set_location_assignment PIN_B3 -to io[4]
set_location_assignment PIN_B4 -to io[5]
set_location_assignment PIN_A4 -to io[6]
set_location_assignment PIN_B5 -to io[7]
set_location_assignment PIN_A5 -to io[8]
set_location_assignment PIN_D5 -to io[9]
set_location_assignment PIN_B6 -to io[10]
set_location_assignment PIN_A6 -to io[11]
set_location_assignment PIN_B7 -to io[12]
set_location_assignment PIN_D6 -to io[13]
set_location_assignment PIN_A7 -to io[14]
set_location_assignment PIN_C6 -to io[15]
set_location_assignment PIN_C8 -to io[16]
set_location_assignment PIN_E6 -to io[17]
set_location_assignment PIN_E7 -to io[18]
set_location_assignment PIN_D8 -to io[19]
set_location_assignment PIN_E8 -to io[20]
set_location_assignment PIN_F8 -to io[21]
set_location_assignment PIN_F9 -to io[22]
set_location_assignment PIN_E9 -to io[23]
set_location_assignment PIN_C9 -to io[24]
set_location_assignment PIN_D9 -to io[25]
set_location_assignment PIN_A8 -to inp[26]
set_location_assignment PIN_B8 -to inp[27]
set_location_assignment PIN_T9 -to inp[28] (..P28)
set_location_assignment PIN_R9 -to inp_resn (PropPlug RESn)
set_location_assignment PIN_E11 -to tio[86] P(58)
set_location_assignment PIN_E10 -to tio[87] (P59)
set_location_assignment PIN_C11 -to tio[88] (P60)
set_location_assignment PIN_B11 -to tio[89] (P61)
set_location_assignment PIN_A12 -to tio[90] (P62 / PropPlug RX)
set_location_assignment PIN_D11 -to tio[91] (P63 / PropPlug TX)

set_location_assignment PIN_B12 -to dac[1] (DAC_0, bit 0..)
set_location_assignment PIN_R12 -to dac[2]
set_location_assignment PIN_T12 -to dac[3]
set_location_assignment PIN_R13 -to dac[4]
set_location_assignment PIN_T13 -to dac[5]
set_location_assignment PIN_T14 -to dac[6]
set_location_assignment PIN_T15 -to dac[7]
set_location_assignment PIN_F13 -to dac[8] (DAC_0, bit ..7)

set_location_assignment PIN_N9 -to dac[10] (DAC_1, bit 0..)
set_location_assignment PIN_P9 -to dac[11]
set_location_assignment PIN_N12 -to dac[12]
set_location_assignment PIN_R10 -to dac[13]
set_location_assignment PIN_P11 -to dac[14]
set_location_assignment PIN_R11 -to dac[15]
set_location_assignment PIN_T10 -to dac[16]
set_location_assignment PIN_T11 -to dac[17] (DAC_1, bit ..7)

set_location_assignment PIN_N16 -to dac[19] (DAC_2, bit 0..)
set_location_assignment PIN_R14 -to dac[20]
set_location_assignment PIN_P16 -to dac[21]
set_location_assignment PIN_P15 -to dac[22]
set_location_assignment PIN_L15 -to dac[23]
set_location_assignment PIN_R16 -to dac[24]
set_location_assignment PIN_K16 -to dac[25]
set_location_assignment PIN_L16 -to dac[26] (DAC_2, bit ..7)

set_location_assignment PIN_J14 -to dac[28] (DAC_3, bit 0..)
set_location_assignment PIN_J16 -to dac[29]
set_location_assignment PIN_K15 -to dac[30]
set_location_assignment PIN_M10 -to dac[31]
set_location_assignment PIN_L13 -to dac[32]
set_location_assignment PIN_L14 -to dac[33]
set_location_assignment PIN_N14 -to dac[34]
set_location_assignment PIN_N15 -to dac[35] (DAC_3, bit ..7)

    You'll need this document to bridge the FPGA pin numbers to the DE0-Nano pinout:

    http://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=593&FID=75023fa36c9bf8639384f942e65a46f3


    Thanks to Chip for the right pin assignments, my R2R ladder is working now.

    I just noticed that SETDACS is not known by PNut_v4.
    I read SETXDAC was renamed to SETDACS !?

  • RaymanRayman Posts: 14,768
    edited 2015-11-11 18:21
    I've had a lot of trouble downloading these files because Antivirus doesn't like pnut...

    But, I just found that if I extract to google drive and then download from google, it's OK with it...

    BTW: 4.3" LCD image code still works with latest version.
  • RaymanRayman Posts: 14,768
    I just hooked P123 up to another computer I use and it wasn't recognized...

    Found it in device manager under "other devices"...
    Looks like I need to do a driver update for FT231X.

    I took a peek at the Prop Tool download page to see if there might be a new version there that had the driver, but that date is 2012, so I don't think it would have a driver for the new FT chip...
  • David BetzDavid Betz Posts: 14,516
    I just loaded the latest FPGA image to my 1-2-3 A7 board and it says "512KB/1024KB Hub RAM". What does that mean? Which is it?
  • potatoheadpotatohead Posts: 10,261
    A7 512 a9 1024, iirc
  • David BetzDavid Betz Posts: 14,516
    potatohead wrote: »
    A7 512 a9 1024, iirc
    Interesting. You mean the same FPGA image will work on both the A7 and the A9? That's surprising.

  • potatoheadpotatohead Posts: 10,261
    I think it has more to do with pnut, and that being helpful info in the version id.
  • David BetzDavid Betz Posts: 14,516
    potatohead wrote: »
    I think it has more to do with pnut, and that being helpful info in the version id.
    Ah, that makes more sense. So I guess the A7 and A9 images both have the same version ID.

  • cgraceycgracey Posts: 14,209
    edited 2015-11-11 19:43
    Rayman wrote: »
    Lots of modes to digest there...

    Saw mention on ADCs. Wasn't sure they were still in the plans...

    Don't immediately see how you can do hsync and vsync for VGA, but I'm sure you have plan...

    For VGA, there are four time-critical channels: R, G, B and HSYNC. There are four DAC channels per cog, which are sufficient. I need to change the FPGA compiles so that DAC0 becomes HSYNC, which is actually a digital signal.
  • RaymanRayman Posts: 14,768
    I'm interested to see how that works.

    BTW: Here's the bird on a fairly new 15" LCD TV (this thing is dirt cheap, but light as a feather and has all the inputs you'd want).
    The image is rock solid with no dot crawl or flicker at all.
    It is fairly pixelated though, which it should be do to low resolution.

    Have to try Bagger's next...



    IMG_0911.JPG
    1280 x 960 - 342K
  • potatoheadpotatohead Posts: 10,261
    That looks pretty good.
  • RaymanRayman Posts: 14,768
    BTW: Nothing beats Photoshop for turning a 24-bit photo to 8-bit indexed bmp (at least as far as I've seen). I think this could look better in certain areas, such as the bird's head...
  • D.PD.P Posts: 790
    For those just joining P2 on a bare DEO nano is there a basic How To: to get the show going. Have the prop plug installed.

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