Going with -A9 won't affect the initial 1-2-3 FPGA deliveries, will it? My understanding is that there are a bunch of boards already made, and they are just waiting for the P2 FPGA image before they will be sold and delivered. I hope we're not talking about delaying this so that the -A9 can be used.
Chip has already said no Solder paste or P&P changes - artwork revisions like this are minimal.
More importantly, the A9 has many advantages
* It is the same device as the BeMicro uses, and many users will want to trial via BeMicro (Google already shows strong SDR activity on the A9, and with WebPack support that eco system will only explode )* The A7 was imposing ceilings on testing, which is never a good idea.
Going with -A9 won't affect the initial 1-2-3 FPGA deliveries, will it? My understanding is that there are a bunch of boards already made, and they are just waiting for the P2 FPGA image before they will be sold and delivered. I hope we're not talking about delaying this so that the -A9 can be used.
Chip has already said no Solder paste or P&P changes - artwork revisions like this are minimal.
More importantly, the A9 has many advantages
* It is the same device as the BeMicro uses, and many users will want to trial via BeMicro (Google already shows strong SDR activity on the A9, and with WebPack support that eco system will only explode )* The A7 was imposing ceilings on testing, which is never a good idea.
What capabilities does the 1-2-3 board provide that are not provided by the BeMicro board? What would I give up by using it?
What kind of clock speed will the P2 on P123 board do?
It's looking like 120MHz right now. Well... that's what a Cyclone IV is doing, anyway. Cyclone V is going to be a little slower. At least 100MHz, let's say.
About the Prop 1-2-3 board:
Daniel and I figured out what to do last night. These Bank 7A pins are actually 1.8V pins (not 3.3V as I said earlier) and they drive the two video DACs (30 data pins to each, plus one clock pin to each). Sixteen of these pins don't exist on the -A9, so what we'll do is common the 30 data pins to each video DAC and keep separate clocks for each. We will clock those DACs on opposite clock edges and mux the data the same way. We should be able make it work by expressing some timing constraints to Quartus. This will leave a net of 14 FPGA I/O's unused, which is no big loss. None of the other circuitry gets disturbed to accommodate the -A9. We'll also put a 16MB flash in place of the current 8MB flash. Those parts have the same footprint.
We'll sell the off the current Prop 1-2-3 boards, but make new ones using the -A9 and bigger flash. So, it's just a minor wiring change on the PCB, two component change-outs and no pick and place or solder stencil changes.
Cool! That makes the current 1-2-3 boards a Limited Edition Collectors Series!!! I say buy one of those while you can still get one. Every Tom, Dick and Harriet P2 tester will end up with one of the common 1-2-3 A9 boards!!
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
Cool! That makes the current 1-2-3 boards a Limited Edition Collectors Series!!! I say buy one of those while you can still get one. Every Tom, Dick and Harriet P2 tester will end up with one of the common 1-2-3 A9 boards!!
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
"1-2-3-CE" signed personally by Chip and Ken. They'll go for millions on eBay!
Cool! That makes the current 1-2-3 boards a Limited Edition Collectors Series!!! I say buy one of those while you can still get one. Every Tom, Dick and Harriet P2 tester will end up with one of the common 1-2-3 A9 boards!!
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
"1-2-3-CE" signed personally by Chip and Ken. They'll go for millions on eBay!
Hey, Ken would be happy if they went for hundreds. I think we've got thirty of them built.
Chip,
Thanks for the update on the Prop-2.
Now that you've changed the design process will we see future versions of the Prop-2 or will you move straight to a Prop-3 after all the bugs are worked out?
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
Table 7: fmax for Nios II Gen2 Processor System (MHz)
Device Family Device used Nios II/f Nios II/e
Cyclone V 5CGXFC7D6F31C6 170 MHz 200 MHz
Cyclone IV EP4CGX30CF19C6 150 MHz 160 MHz
Max 10 10M50DFF672I6G 270 MHz 330 MHz
Table 8: MIPS for Nios II Gen2 Processor System
Device Family Nios II/f Nios II/e
Cyclone V 181 30
Cyclone IV GX 181 26
Table 11: LE Usage for Nios II Gen2 Cyclone V, IV GX, MAX 10
Processor Core Nios II/f Nios II/e
Cyclone V (ALMs) 810 311
Cyclone IV GX 2291 768
MAX 10 (logic cells) 2275 788
Chip,
Best you check Altera are going to give you a good price on those A9's.
And what are you paying for the Flash parts. The Altera Flash parts are very expensive. I've seen that alternate Flash offerings are orders of magnitudes cheaper if they can be used. eg S25FLxxx
We'll sell the off the current Prop 1-2-3 boards, but make new ones using the -A9 and bigger flash. So, it's just a minor wiring change on the PCB, two component change-outs and no pick and place or solder stencil changes.
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure. At the moment, customers aren't happy with our release of raw food (ahem, these forums). It's easier to give them away if that removes expectations for any support. . .
Ken Gracey
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure.
The documentation could be managed as build-variants, and thus simply piggyback on the time needed to release any FPGA board. Chip has a table of A7<->A9 changes already, and if you generate a netlist / Pin map from each build variant, that, with the A9 final DOCs should be enough.
A bigger issue may be providing P2 image builds for multiple FPGAs, tho some work done on P1V may help there ?
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure. At the moment, customers aren't happy with our release of raw food (ahem, these forums). It's easier to give them away if that removes expectations for any support. . .
Ken Gracey
Ok Ken lets try and solve this, because they'll gather dust, and an A7 would fit a mighty impressive P1V application, and there's not that much time to the osh summit.
Plus it would be good to start developing some community hardware plug-ins for the memory port and those 3 edge ports, which will all work with the A9 just as nicely as the A7.
So how about a free 1-2-3 A7 to with $xxx worth of parallax gear from the shop? For "early experimenters" wanting to get P1V stuff going. Call it the 1-2-Free deal. That way you don't even have to list it in the shop. Just name the $xxx threshold (several hundreds)
BTW we don't really need/expect support on something like this, in fact we expect a few issues that can be shared/sorted by the community.
I'm pretty sure that if the 1-2-3 A7 boards were released into the wild (community) they would be snapped up in no time. I don't think you need to worry about them collecting dust. They all can be put to good use immediately.
Said with hand in air waving credit card!
I have to admit, all this good news about the BeMicro A9 and putting the A9 on the 1-2-3 board is kinda alleviating the forum pains. Thanks Chip and Ken!
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
Table 7: fmax for Nios II Gen2 Processor System (MHz)
Device Family Device used Nios II/f Nios II/e
Cyclone V 5CGXFC7D6F31C6 170 MHz 200 MHz
Cyclone IV EP4CGX30CF19C6 150 MHz 160 MHz
Max 10 10M50DFF672I6G 270 MHz 330 MHz
Table 8: MIPS for Nios II Gen2 Processor System
Device Family Nios II/f Nios II/e
Cyclone V 181 30
Cyclone IV GX 181 26
Table 11: LE Usage for Nios II Gen2 Cyclone V, IV GX, MAX 10
Processor Core Nios II/f Nios II/e
Cyclone V (ALMs) 810 311
Cyclone IV GX 2291 768
MAX 10 (logic cells) 2275 788
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
Table 7: fmax for Nios II Gen2 Processor System (MHz)
Device Family Device used Nios II/f Nios II/e
Cyclone V 5CGXFC7D6F31C6 170 MHz 200 MHz
Cyclone IV EP4CGX30CF19C6 150 MHz 160 MHz
Max 10 10M50DFF672I6G 270 MHz 330 MHz
Table 8: MIPS for Nios II Gen2 Processor System
Device Family Nios II/f Nios II/e
Cyclone V 181 30
Cyclone IV GX 181 26
Table 11: LE Usage for Nios II Gen2 Cyclone V, IV GX, MAX 10
Processor Core Nios II/f Nios II/e
Cyclone V (ALMs) 810 311
Cyclone IV GX 2291 768
MAX 10 (logic cells) 2275 788
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
P.S. I downloaded V15.0 of Quartus II and, indeed, there are all the -A9 options available.
Chip,
Thanks for the update on the Prop-2.
Now that you've changed the design process will we see future versions of the Prop-2 or will you move straight to a Prop-3 after all the bugs are worked out?
I don't know yet. It depends on how things go, I guess.
I really hope that all this talk about -A9 and future version of the Prop don't slow down progress on the P2. It seems like the 1-2-3 FPGA board with the -A7 is ready to be shipped, and the P2 FPGA image is almost done. I would rather see this become a reality instead of thinking about what happens after the P2.
I really hope that all this talk about -A9 and future version of the Prop don't slow down progress on the P2. It seems like the 1-2-3 FPGA board with the -A7 is ready to be shipped, and the P2 FPGA image is almost done. I would rather see this become a reality instead of thinking about what happens after the P2.
From what Chip said, the A7 was not quite fitting a full P2, so the move to A9 should accelerate release date, rather than delay it, as it avoids fractional build compromises/delays in testing.The PCB changes are minimal, and another A9 FPGA board already exists, as BeMicro CV A9.
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
Sometimes know where to set the targets speeds can help :)The Altera MIPs numbers do not align perfectly with their MHz table in the same document, but the relative MAX 10 speed was interesting. (270MHz vs 170MHz @ NIOS II/f)
If you need a speed boost to match final silicon speeds, for 100% speed SW running, (in reduced COGs) then the MAX10 could be a pathway. Examples may be SW coded USB.I see 08 and 50 sized Boards are now available in MAX10.
I really hope that all this talk about -A9 and future version of the Prop don't slow down progress on the P2. It seems like the 1-2-3 FPGA board with the -A7 is ready to be shipped, and the P2 FPGA image is almost done. I would rather see this become a reality instead of thinking about what happens after the P2.
This has been less than a day's diversion for me, and Daniel's handling the rest of it. I'm still working on the Prop2.
Ken,
I agree with ozpropdev. Sell the A7 boards, at least for something. I know that is miniscule compared with its development costs.
Did you get a price on the A9 ? Hope Altera give you good pricing!
Chip,
Yes, the Cyclone V takes a lot loooonger to compile than for Cyclone IV. You will need to option out some of the complexities for testing (like only compile 4 cogs, no VGA etc)
What makes the Prop II unique or superior? I still believe: it is the genius equipped with the PII. So aside of this, the genius should take a look at the analog IO features, compared to the MAX11300, for example, a chip that is in the same price range and dump like a bread. (not to insult the bread)
m00tykins said:
...
Thanks for the update, Chip! I hope you don't have to struggle with tools too much going forward and get a chance to work on the fun stuff!
What did chip say?
This new forum software always reverts to showing high voted posts first. So they aren't in dated order until you explicitly select it at the tail end of the opening post. Each time you come back you'll have to reselect "Date Added" on each and every topic.
If you look down the P2 thread history you'll see I've made a few threads about porting a large operating system to the P2 once it's out. Since then I've been reconsidering the requirements for making this feasible, and a microkernel is really the only way to go if you're trying to port an OS... So I'm going to try porting Minix once the P2 is out, since the Minix 3 kernel is "only" 6,000 LoC. However, once again, this hinges on whether or not the P2 can be fitted with an MMU/MPU. I *think* the only other thing really necessary for a modern OS isn't actually a MMU, but memory protection (a MPU), since other memory management can still be done in software.
Last time the prospect was brought up I was told the P2 will not have an MMU. Is this still the case chip- no MMU or MPU? And do you guys think hubexec/a cog could give at least the functionality of a MPU?
I'm not sure if that counts as a newbie question or not, but either way, thanks for your patience! XD
Comments
Chip has already said no Solder paste or P&P changes - artwork revisions like this are minimal.
More importantly, the A9 has many advantages
* It is the same device as the BeMicro uses, and many users will want to trial via BeMicro (Google already shows strong SDR activity on the A9, and with WebPack support that eco system will only explode )* The A7 was imposing ceilings on testing, which is never a good idea.
Chip has already said no Solder paste or P&P changes - artwork revisions like this are minimal.
More importantly, the A9 has many advantages
* It is the same device as the BeMicro uses, and many users will want to trial via BeMicro (Google already shows strong SDR activity on the A9, and with WebPack support that eco system will only explode )* The A7 was imposing ceilings on testing, which is never a good idea.
What capabilities does the 1-2-3 board provide that are not provided by the BeMicro board? What would I give up by using it?
It's looking like 120MHz right now. Well... that's what a Cyclone IV is doing, anyway. Cyclone V is going to be a little slower. At least 100MHz, let's say.
About the Prop 1-2-3 board:
Daniel and I figured out what to do last night. These Bank 7A pins are actually 1.8V pins (not 3.3V as I said earlier) and they drive the two video DACs (30 data pins to each, plus one clock pin to each). Sixteen of these pins don't exist on the -A9, so what we'll do is common the 30 data pins to each video DAC and keep separate clocks for each. We will clock those DACs on opposite clock edges and mux the data the same way. We should be able make it work by expressing some timing constraints to Quartus. This will leave a net of 14 FPGA I/O's unused, which is no big loss. None of the other circuitry gets disturbed to accommodate the -A9. We'll also put a 16MB flash in place of the current 8MB flash. Those parts have the same footprint.
We'll sell the off the current Prop 1-2-3 boards, but make new ones using the -A9 and bigger flash. So, it's just a minor wiring change on the PCB, two component change-outs and no pick and place or solder stencil changes.
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
Looking forward to dusting off my DE2-115 & other fpga boards
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
"1-2-3-CE" signed personally by Chip and Ken. They'll go for millions on eBay!
If Chip signs them, then you have a Limited Edition Signature Series.....Woo Hoo!! (You can get premium pricing for those babies!)
{no worries, just trying to help out the marketing folks and clear a little inventory!)
"1-2-3-CE" signed personally by Chip and Ken. They'll go for millions on eBay!
Hey, Ken would be happy if they went for hundreds. I think we've got thirty of them built.
Thanks for the update on the Prop-2.
Now that you've changed the design process will we see future versions of the Prop-2 or will you move straight to a Prop-3 after all the bugs are worked out?
I found these speeds on a new Altera Nios spec sheet
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ds/ds_nios2_perf.pdf
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
Best you check Altera are going to give you a good price on those A9's.
And what are you paying for the Flash parts. The Altera Flash parts are very expensive. I've seen that alternate Flash offerings are orders of magnitudes cheaper if they can be used. eg S25FLxxx
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure. At the moment, customers aren't happy with our release of raw food (ahem, these forums). It's easier to give them away if that removes expectations for any support. . .
Ken Gracey
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure.
The documentation could be managed as build-variants, and thus simply piggyback on the time needed to release any FPGA board. Chip has a table of A7<->A9 changes already, and if you generate a netlist / Pin map from each build variant, that, with the A9 final DOCs should be enough.
A bigger issue may be providing P2 image builds for multiple FPGAs, tho some work done on P1V may help there ?
We should probably think this over a bit. Putting them into a sellable condition will require about 40+ hrs of documentation from Jeff and Daniel - count on two weeks to be sure. At the moment, customers aren't happy with our release of raw food (ahem, these forums). It's easier to give them away if that removes expectations for any support. . .
Ken Gracey
Ok Ken lets try and solve this, because they'll gather dust, and an A7 would fit a mighty impressive P1V application, and there's not that much time to the osh summit.
Plus it would be good to start developing some community hardware plug-ins for the memory port and those 3 edge ports, which will all work with the A9 just as nicely as the A7.
So how about a free 1-2-3 A7 to with $xxx worth of parallax gear from the shop? For "early experimenters" wanting to get P1V stuff going. Call it the 1-2-Free deal. That way you don't even have to list it in the shop. Just name the $xxx threshold (several hundreds)
BTW we don't really need/expect support on something like this, in fact we expect a few issues that can be shared/sorted by the community.
Said with hand in air waving credit card!
===Jac
I found these speeds on a new Altera Nios spec sheet
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ds/ds_nios2_perf.pdf
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
I found these speeds on a new Altera Nios spec sheet
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ds/ds_nios2_perf.pdf
Seems on their Speed-optimized (/f) model, Cyclone V is ~ 1.13x faster (MHz) than Cyclone IV, and the MAX 10 is an impressive 1.80x speed of Cyclone IV
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
P.S. I downloaded V15.0 of Quartus II and, indeed, there are all the -A9 options available.
Thanks for the update on the Prop-2.
Now that you've changed the design process will we see future versions of the Prop-2 or will you move straight to a Prop-3 after all the bugs are worked out?
I don't know yet. It depends on how things go, I guess.
From what Chip said, the A7 was not quite fitting a full P2, so the move to A9 should accelerate release date, rather than delay it, as it avoids fractional build compromises/delays in testing.The PCB changes are minimal, and another A9 FPGA board already exists, as BeMicro CV A9.
I would hope that the Cyclone V would be faster than the IV, but in my early tests it compiled to a slower Fmax. It could be that they've improved the logic mapping algorithm since I had that experience. I remember (as will some of you) that it took waaaaaay longer to compile a Prop2-Hot cog for a Cyclone V than it did for a IV.
Thanks for the data, jmg.
Sometimes know where to set the targets speeds can help :)The Altera MIPs numbers do not align perfectly with their MHz table in the same document, but the relative MAX 10 speed was interesting. (270MHz vs 170MHz @ NIOS II/f)
If you need a speed boost to match final silicon speeds, for 100% speed SW running, (in reduced COGs) then the MAX10 could be a pathway. Examples may be SW coded USB.I see 08 and 50 sized Boards are now available in MAX10.
This has been less than a day's diversion for me, and Daniel's handling the rest of it. I'm still working on the Prop2.
I agree with ozpropdev. Sell the A7 boards, at least for something. I know that is miniscule compared with its development costs.
Did you get a price on the A9 ? Hope Altera give you good pricing!
Chip,
Yes, the Cyclone V takes a lot loooonger to compile than for Cyclone IV. You will need to option out some of the complexities for testing (like only compile 4 cogs, no VGA etc)
...
Thanks for the update, Chip! I hope you don't have to struggle with tools too much going forward and get a chance to work on the fun stuff!
What did chip say?
m00tykins said:
...
Thanks for the update, Chip! I hope you don't have to struggle with tools too much going forward and get a chance to work on the fun stuff!
What did chip say?
This new forum software always reverts to showing high voted posts first. So they aren't in dated order until you explicitly select it at the tail end of the opening post. Each time you come back you'll have to reselect "Date Added" on each and every topic.
On another note:
If you look down the P2 thread history you'll see I've made a few threads about porting a large operating system to the P2 once it's out. Since then I've been reconsidering the requirements for making this feasible, and a microkernel is really the only way to go if you're trying to port an OS... So I'm going to try porting Minix once the P2 is out, since the Minix 3 kernel is "only" 6,000 LoC. However, once again, this hinges on whether or not the P2 can be fitted with an MMU/MPU. I *think* the only other thing really necessary for a modern OS isn't actually a MMU, but memory protection (a MPU), since other memory management can still be done in software.
Last time the prospect was brought up I was told the P2 will not have an MMU. Is this still the case chip- no MMU or MPU? And do you guys think hubexec/a cog could give at least the functionality of a MPU?
I'm not sure if that counts as a newbie question or not, but either way, thanks for your patience! XD