I was going to start another post, however this sort of dovetails nicely.
I was going to say that a re-examination of the P2 Req's should start with an immediate release of a P2 image, and someone sticking a pin in a date 4-6 months from now as a tentative tape out date.
Unless I'm mistaken, which I may be, the promised P2 FPGA test image still hasn't been released since before Dec?
As has been noted many times, the enemy of good is perfection.
'twould seem to me that unless it were a gigantic broken mess, even a crippled P2 image would allow for substantial testing to take place by many here. Seems like a waste of free, useful resources that. Along with time.
As far as pinning a date, I think the results of not doing such are abundantly clear. Personally, I'd be pretty concerned when a key employee has to be let go because revenue can not support both him and a product license.
Given the latest statements from Ken and Chip I'm hoping for the first FPGA image by June and a "final" version by December. If this happens we might see silicon in early 2016. If this doesn't happen then Parallax may want to ditch the P2 altogether. Instead of building their own chip they could adapt somebody else's chip, and produce boards and software that are consistent with the Parallax way of thinking.
Instead of building their own chip they could adapt somebody else's chip, and produce boards and software that are consistent with the Parallax way of thinking.
Maybe it is time for Chip to go back to his development roots, Microchip PIC chip(s). I bet he could do wonders with the Microchip PIC32MX170F256, as a starting point, and have something for us in less than 6 months. The innovation, create some software cores so it resembles the propeller... and the rest would be history.
re:: Is it time to re-examine the P2 requirements ???
Every time I see a thread like this I think that I'm stuck in the twilight zone and can't wait to wake up. LOL
There have been too many threads like this, and too much attention paid to them. Perfectionism, focus on fantastic leaps rather than incremental improvements, too many cooks in the kitchen, .... so on... have all but killed the thing already.
If this happens we might see silicon in early 2016. If this doesn't happen then Parallax may want to ditch the P2 altogether. Instead of building their own chip they could adapt somebody else's chip, and produce boards and software that are consistent with the Parallax way of thinking.
Considering where it's at now and all that's gone before, I expect it will be 2017 before chips are available for design-in: a milestone which, even if achieved, may by then be an exercise in futility.
Holy Smile! One moment you're say this thread is worthless for it's input, then next you are saying the Prop2 isn't worth pursuing. Talk about two faced!
Holy Smile! One moment you're say this thread is worthless for it's input, then next you are saying the Prop2 isn't worth pursuing. Talk about two faced!
Go back and read again. A near complete, and rather immature, mis-representation/-understanding of what was said. Holy Smile indeed.
I will give this thread's OP by Cluso99 credit: the recommendations within are realistic and practical, little or none of the pie-in-the-sky business that has done far more harm than good. Not so much a re-examination, though -- for some have been saying as much for a long while.
I think the BS3 ship already sailed unless you can come up with a FREE microcontroller oriented BASIC that is rooted in GW-BASIC and runs on a $5 PIC32MX170 28 pin PDIP. I won't go into more detail in respect for our host but look for MicroMite MK II if you want more details.
Whist I was waiting for the P2 I had nothing to do and got bored. So I made my own.
Well, the FPGA is a bit rich for my blood, so I went with a RPi 2 and looking at the bare metal forum to see how possible it would be to run Core0 as RTOS primary and Core1-3 as Cog-like secondaries.
Wow, this thread is over a month old!! Time flies when you're speculating and commenting from the sidelines!!
I guess it is time to re-examine the proposed requirements we were asked to consider as part of our re-examination:
Why not a P2 as follows...
1. 8-16 P1 COGs with
(a) Additional MUL and possibly DIV instructions
(b) Additional JMPRET relative instruction
(c) Additional indirect R/W memory instruction or AUGDS instruction
(d) 1 or 2 COGs with 32KB Cog Ram (for a pseudo hubexec using relative JMPRET)
- remember cog ram is still only single port so extra memory is easily accessed indirectly
(e) instruction clocks as per P1 (4 clocks per instruction as normal)
2. 128KB-256KB Hub Ram
(a) Single cycle access if possible (P1 was 2 cycle)
- no wide access, etc.
3. Minimal Boot ROM as per P2
(a) Small boot to load SPI FLASH and/or simple monitor
(b) Spin Interpreter to be soft-loaded from spi flash
4. 48-64 I/O
(a) 84 QFP package 0.8mm pitch if poss.
(b) 8 pins with simple ADC only if possible, otherwise no ADC (use sigma-delta as P1)
5. 160-200MHz
(a) 2x P1 speed
This should be possible to do quite quickly and would relieve the pressure on the P2.
First off, I think we need to better define "quite quickly". This past month seems to have gone quite quickly. I've actually accomplished a lot at work. From a hobbyist perspective, I've: embraced the RasPi2 and built up several systems; experimented with UBS connected hard drives; investigated Parallax tool deployment; generally increased my overall knowledge of RasPi; started playing with FPGSs again (Xilinx Spartans from GadgetFactory); cleaned up my Windows Laptop; dabbled a bit more with Espruino; and things I've already forgotten. Quite a bit accomplished in a time that went "quite quickly"
So, again, I say we need to define "quite quickly" because as far as we have seen, there has been no movement on the P2 front or on any interim device that could be done "quite quickly". So, as time passes, I will once again re-examine my requirements and sally forth into the ever expanding playground that this hobby puts in your path!! Someday, I hope to see a P2 or even just a P2 image ready for FPGA testing in my path.....someday, "quite quickly"??
OK, it's a fair cop, there is no such thing. My home made P2 is all in my imagination. Despite the fact I have been told elsewhere on this forum that I don't have one.
On a more serious note...
Perhaps at this stage of computing history it's time for people to stop inventing instructions sets for their new processors.
The P2 instruction set, whatever it is now, should be abandoned.
It should be replaced by the RISC V instruction set architecture as specified by the University of California, Berkeley.
At it's base level RISC V is only 40 simple instructions. RISC V already has GCC to support it. RISC V supports extensions to the ISA, for example whatever special things a P2 hardware needs, RISC V scales to 64 and even 128 bits that will be in demand in the not so distant future. RISC V has the backing of many companies in embedded, mobile, phone development that want to get away from Intel and ARM. An example of RISC V, the LowRISC, will become available via some guys involved with the Raspberry Pi Foundation in a year or so.
If you want to see a general introduction as to why this is a good idea watch this by Krste Asanović from UC Berkeley at the first RISC workshop: https://www.youtube.com/watch?v=A5kpo_ff98M[url]
and this from Alex Bradbury of Cambridge about the, perhaps Raspberry Pi, RISC V machine: [/url]https://www.youtube.com/watch?v=r1i9SAOdyS4 due out in about a year.
I agree that RISC V and LowRISC seem very interesting. It would be interesting to see how Chip would make use of extensions to add Propeller-like features. Not having to worry about things like hub exec and task switching would leave him more time to add Propeller/Parallax magic in the form of RISC V extensions. Sounds like a good plan. Also, I think the LowRISC chip is supposed to be fabricated in either 40nm or 25nm. Not sure how that would affect power requirements but it will certainly outperform a 180nm P2 and the minion processors have some of the same deterministic features of the COG.
...sally forth into the ever expanding playground that this hobby puts in your path.
What a great turn of phrase.
As a huge supporter of Parallax and Chip's ideals in system design I could see this trend as worrying.
Not only do we have an "ever expanding playground" it seems to be expanding faster and faster. Not just for hobbyists either.
Since we have been waiting on the P2 we have had:
1) The Raspeberry Pi
2) The new Raspberry Pi, multi-core and all.
3) The Esruino and the Micro Python or even just the STM32 F4.
4) Recently the tiny ultra cheap ESP8266 WIFI devices which are also powerful processors in their own right. No extra MCU required.
5) Heck, today I'm ordering an 8 core 64 bit ARM device for a hundred bucks or so.
6) And so on.
Now, I would always argue that those other MCUs cannot do what a P1 can do in some application areas. I would hope that is even more true of the P2.
Problem is, those unique application areas are vanishing rapidly.
Hence my suggestion to abandon ship and adopt the RISC V instruction set. Get in with the new frontier of open standard hardware that I strongly suspect RISC V will foster. Wrap the RISC V around with Propeller I/O simplicity and goodness.
Of course I realize this is not going to happen. The P2 is too far down the road for that.
...the minion processors have some of the same deterministic features of the COG.
Exactly. I did not mention the minion processors. A very COG like concept. No doubt using the RISC V instruction set. (Hey, where do you think I got the idea for these posts from )
Alex Bradbury in the LowRISC presentation video I linked above describes the forthcoming LowRISC board as "A Raspberry Pi for grown ups". This is very telling in my mind.
Given that Alex is very much involved with the Raspberry Pi Foundation it leads me to speculate that in a year or two's time there may well be a new LowRISC Raspberry Pi.
And you know how successful they have been at gaining mind share and shipping millions of units.
3) The Esruino and the Micro Python or even just the STM32 F4.
4) Recently the tiny ultra cheap ESP8266 WIFI devices which are also powerful processors in their own right. No extra MCU required.
5) Heck, today I'm ordering an 8 core 64 bit ARM device for a hundred bucks or so.
6) And so on.
And that hardly scratches the surface. One could rattle off a half-dozen more without much trouble (not to be overlooked, the expanding Cypress PSoC line).
I think "quite quickly" means a time frame that doesn't allow Parallax to become utterly irrelevant, or worse yet belly-up.
The P2 will be whatever Chip thinks it should be. This thread is somewhat pointless because I think that Chip is ignoring the forum these days, and is busy working on getting the FPGA image out ASAP. I'm sure that Ken and Chip know that the future of Parallax depends on the P2, and I think they are serious about having the get-together in the Fall and having a complete P2 FPGA image by that time. As I said before, in order to achieve this goal they need to have an initial P2 FPGA image by June. It could come sooner, but I'm expecting it in June.
Comments
Every time I see a thread like this I think that I'm stuck in the twilight zone and can't wait to wake up. LOL
Yes, it's like Groundhog Day all over again. If you see what I mean.
I was going to say that a re-examination of the P2 Req's should start with an immediate release of a P2 image, and someone sticking a pin in a date 4-6 months from now as a tentative tape out date.
Unless I'm mistaken, which I may be, the promised P2 FPGA test image still hasn't been released since before Dec?
As has been noted many times, the enemy of good is perfection.
'twould seem to me that unless it were a gigantic broken mess, even a crippled P2 image would allow for substantial testing to take place by many here. Seems like a waste of free, useful resources that. Along with time.
As far as pinning a date, I think the results of not doing such are abundantly clear. Personally, I'd be pretty concerned when a key employee has to be let go because revenue can not support both him and a product license.
Ray
There have been too many threads like this, and too much attention paid to them. Perfectionism, focus on fantastic leaps rather than incremental improvements, too many cooks in the kitchen, .... so on... have all but killed the thing already.
Considering where it's at now and all that's gone before, I expect it will be 2017 before chips are available for design-in: a milestone which, even if achieved, may by then be an exercise in futility.
re:Yes, it's like Groundhog Day all over again. If you see what I mean.
Yes unfortunately I do know what you mean LOL
Any word on the P5 yet?
Well, the FPGA is a bit rich for my blood, so I went with a RPi 2 and looking at the bare metal forum to see how possible it would be to run Core0 as RTOS primary and Core1-3 as Cog-like secondaries.
Quite so. My home made P2 is many orders of magnitude bigger than you might expect and correspondingly power hungry.
It's probably better I don't publish the details
I guess it is time to re-examine the proposed requirements we were asked to consider as part of our re-examination:
First off, I think we need to better define "quite quickly". This past month seems to have gone quite quickly. I've actually accomplished a lot at work. From a hobbyist perspective, I've: embraced the RasPi2 and built up several systems; experimented with UBS connected hard drives; investigated Parallax tool deployment; generally increased my overall knowledge of RasPi; started playing with FPGSs again (Xilinx Spartans from GadgetFactory); cleaned up my Windows Laptop; dabbled a bit more with Espruino; and things I've already forgotten. Quite a bit accomplished in a time that went "quite quickly"
So, again, I say we need to define "quite quickly" because as far as we have seen, there has been no movement on the P2 front or on any interim device that could be done "quite quickly". So, as time passes, I will once again re-examine my requirements and sally forth into the ever expanding playground that this hobby puts in your path!! Someday, I hope to see a P2 or even just a P2 image ready for FPGA testing in my path.....someday, "quite quickly"??
On a more serious note...
Perhaps at this stage of computing history it's time for people to stop inventing instructions sets for their new processors.
The P2 instruction set, whatever it is now, should be abandoned.
It should be replaced by the RISC V instruction set architecture as specified by the University of California, Berkeley.
At it's base level RISC V is only 40 simple instructions. RISC V already has GCC to support it. RISC V supports extensions to the ISA, for example whatever special things a P2 hardware needs, RISC V scales to 64 and even 128 bits that will be in demand in the not so distant future. RISC V has the backing of many companies in embedded, mobile, phone development that want to get away from Intel and ARM. An example of RISC V, the LowRISC, will become available via some guys involved with the Raspberry Pi Foundation in a year or so.
See here: http://riscv.org/
If you want to see a general introduction as to why this is a good idea watch this by Krste Asanović from UC Berkeley at the first RISC workshop: https://www.youtube.com/watch?v=A5kpo_ff98M[url]
and this from Alex Bradbury of Cambridge about the, perhaps Raspberry Pi, RISC V machine: [/url]https://www.youtube.com/watch?v=r1i9SAOdyS4 due out in about a year.
$189 for an FPGA version might be fun to play with.
Hey, thanks, Heater for tossing another shiny object in my path!!
As a huge supporter of Parallax and Chip's ideals in system design I could see this trend as worrying.
Not only do we have an "ever expanding playground" it seems to be expanding faster and faster. Not just for hobbyists either.
Since we have been waiting on the P2 we have had:
1) The Raspeberry Pi
2) The new Raspberry Pi, multi-core and all.
3) The Esruino and the Micro Python or even just the STM32 F4.
4) Recently the tiny ultra cheap ESP8266 WIFI devices which are also powerful processors in their own right. No extra MCU required.
5) Heck, today I'm ordering an 8 core 64 bit ARM device for a hundred bucks or so.
6) And so on.
Now, I would always argue that those other MCUs cannot do what a P1 can do in some application areas. I would hope that is even more true of the P2.
Problem is, those unique application areas are vanishing rapidly.
Hence my suggestion to abandon ship and adopt the RISC V instruction set. Get in with the new frontier of open standard hardware that I strongly suspect RISC V will foster. Wrap the RISC V around with Propeller I/O simplicity and goodness.
Of course I realize this is not going to happen. The P2 is too far down the road for that.
Alex Bradbury in the LowRISC presentation video I linked above describes the forthcoming LowRISC board as "A Raspberry Pi for grown ups". This is very telling in my mind.
Given that Alex is very much involved with the Raspberry Pi Foundation it leads me to speculate that in a year or two's time there may well be a new LowRISC Raspberry Pi.
And you know how successful they have been at gaining mind share and shipping millions of units.
I think "quite quickly" means a time frame that doesn't allow Parallax to become utterly irrelevant, or worse yet belly-up.