Is it time to re-examine the P2 requirements ???
Cluso99
Posts: 18,069
There seems to be so many unknowns (and therefore probably risks) in the smart pins that the timeline is blowing out again.
Is now the time right to spec a lower version P2 with minimal risks that will be quicker to market, and satisfy many at the same time ???
Why not a P2 as follows...
1. 8-16 P1 COGs with
(a) Additional MUL and possibly DIV instructions
(b) Additional JMPRET relative instruction
(c) Additional indirect R/W memory instruction or AUGDS instruction
(d) 1 or 2 COGs with 32KB Cog Ram (for a pseudo hubexec using relative JMPRET)
- remember cog ram is still only single port so extra memory is easily accessed indirectly
(e) instruction clocks as per P1 (4 clocks per instruction as normal)
2. 128KB-256KB Hub Ram
(a) Single cycle access if possible (P1 was 2 cycle)
- no wide access, etc.
3. Minimal Boot ROM as per P2
(a) Small boot to load SPI FLASH and/or simple monitor
(b) Spin Interpreter to be soft-loaded from spi flash
4. 48-64 I/O
(a) 84 QFP package 0.8mm pitch if poss.
(b) 8 pins with simple ADC only if possible, otherwise no ADC (use sigma-delta as P1)
5. 160-200MHz
(a) 2x P1 speed
This should be possible to do quite quickly and would relieve the pressure on the P2.
Thoughts???
Is now the time right to spec a lower version P2 with minimal risks that will be quicker to market, and satisfy many at the same time ???
Why not a P2 as follows...
1. 8-16 P1 COGs with
(a) Additional MUL and possibly DIV instructions
(b) Additional JMPRET relative instruction
(c) Additional indirect R/W memory instruction or AUGDS instruction
(d) 1 or 2 COGs with 32KB Cog Ram (for a pseudo hubexec using relative JMPRET)
- remember cog ram is still only single port so extra memory is easily accessed indirectly
(e) instruction clocks as per P1 (4 clocks per instruction as normal)
2. 128KB-256KB Hub Ram
(a) Single cycle access if possible (P1 was 2 cycle)
- no wide access, etc.
3. Minimal Boot ROM as per P2
(a) Small boot to load SPI FLASH and/or simple monitor
(b) Spin Interpreter to be soft-loaded from spi flash
4. 48-64 I/O
(a) 84 QFP package 0.8mm pitch if poss.
(b) 8 pins with simple ADC only if possible, otherwise no ADC (use sigma-delta as P1)
5. 160-200MHz
(a) 2x P1 speed
This should be possible to do quite quickly and would relieve the pressure on the P2.
Thoughts???
Comments
While I was saddened by the demise of the last P2 (cried into my beer for a while
I for one am quite happy with the new streamlined specification and feel it's a good balance of performance and features.
I am certainly encouraged by Chip's comments in his last thread.
With the introduction of Parallax's own FPGA board around the corner and the addition of more FPGA
platforms for testing (DE2-115,DE0-Nano,BeMicro CV,and maybe the BeMicro Max10?) this opens the
door to larger population of testers.
In the meantime I'll sit here fingers crossed pressing "Refresh" in my browser.....Refresh......Refresh
Cheers
Brian
It would need to have the same very low power curve as the existing Prop1. To that end we are talking the same 300nm process I suspect. Max speed would be defined by this.
It would be Prop1 binary compatible and have no asymmetries. This means 4 clocks per instruction, 16 clocks per rotation, no special Cogs, similar ROM located at 32KB mark, and any additional instructions must fit the existing encodings. SPI booting would be okay due to it being a new footprint.
Port B is obvious bonus. 16 Cogs would be cool but more HubRAM is priority for real-estate use.
Anyone here is completely free to prototype using the P1 code base. That is what it is there for.
Get something compelling, and there can be discussion on having it produced.
-Phil
Besides, who here can honestly say that they've run out of interesting things for the P1 to do?
-Phil
In the 6-7 years I have been playing with the P1, more and more I am finding I need more RAM, and not just double (ie 64KB). I don't need the ROM except to boot.
There are now plenty of chips with large RAM with which to choose. None are like the P1 but ultimately if a P1 won't cut the ice it doesn't matter. The market does not stand still.
IMHO the P1 needs a bigger cousin now! Not next year or the one after that!
Getting Parallax to fund that, would involve considerable mask costs, and what staff would oversee the testing ?
Nothing in that list looks like a "re-examine the P2 requirements", nor is it a P2.
Given the P1V exists already, and FPGA and CPLD are getting cheaper, another approach for those wanting a P1.5 or P1.65 or whatever, is to map out the FPGA price curves, and "how many COGS/RAM" of a P1V++ can fit into each one.
eg I have not seen any numbers done yet for Altera MAX 10, their new 55nm Flash family, with a wide range of Logic choices, and a common package across many.
The 10M08 looks to support 49K bytes RAM and 201K Bytes user FLASH, & 24 18x18 Multipliers, price in the $10~20 region.
The 180nm manufacturing node, does not need 'process proving' - it is a mature and now trailing edge process node.
The Parallax PCB is a large FPGA at the higher price end, and focuses on P2+ development.
The BeMicroMAX10 is certainly interesting for P1.5+ / P1V work. That's a very modern 55nm Flash node.
http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#RJQn
Shows 355 in stock, at $30 each, for a
10M08DAF484C8GES FPGA Evaluation Kit 24MHz/50MHz CPU 8MB RAM 256Kb Flash
FPGA boards can be bought up right now using P1V, so they are better in the
Propeller 1 Verilog Code Development thread.
Parallax is a business and the Gracy family has to lead the way in deciding how to best deploy their capital for the prosperity of themselves and their employees.
I wish them the best of luck in doing so. The Propeller 1 was sucessful in part because it was a complete surprise to most of us. I am willing to accept the same with the Propeller 2 rather than lobby for whatever fantasy goodie I desire today... but may not tomorrow.
AND, I too certainly have more than enough to do and learn with the P1.
I feel the best thing at this time is for all of us to keep very quite and let the magic happen.
Our worst nightmare is that the magic never happens but throwing ideas into the pot now is not going to help.
We are done with the advice from the forum thing. It was frantic, it was interminable, it did not work. Perhaps some of those ideas and suggestions live on in whatever is cooking now. Let's wait and see.
Clusso, didn't you start a similar thread with P2 suggestions just a couple of weeks ago? And didn't it get much the same responses? Did I imagine that?
Anyway, meanwhile I have to buy a tube of DIP Propellers 1's. Some how it has come to pass that I can't lay my hands on a Prop in this house at all!
Not me. I haven't been following the P2 development at all. Too many P1 projects in the pipeline. Of course I thought the same thing when I migrated from the BS2 to the P1.
Very true. Many semi vendors have a cornerstone client ( or a few) lined up when they develop a new die - more so if that new die is not mainstream or incremental.
The increasing tie-up with OnSemi may lead in interesting directions.
Chip is off in his corner working on what he thinks should be the P2.
This is NOT the time to pull /RST_CHIP low again!
We already have had too many restarts, heck I really wish the "hot" chip had just been made. We could have been running it for a few months, and the <1W people could just have run it at 100MHz.
Ive seen too many instances of people wanting to throw out the baby with the bathwater already.
If you just want a simple P1+, change the verilog and use an FPGA.
Others (like me) want/need more, and Chip has many times he stated he wants more.
Enough redesigns already.
However, the "lazy Susan" 16-channel simultaneous "bank switching" (HUB 2.0) design would most likely be retained, as that's something that ultimately needs testing in that it's on the radical side and highly desired from the throughput standpoint. Of course, all of the features I've casually and likely selfishly left out are highly desirable, but I'm starting to fear that the design of the smart pins/custom stuff (and maybe HUB exec) is going to push this chip into 2016.
I recall that the proposed P2 design (16/64/512) was something that was envisioned to be doable in "short order," but, understandably, the devil is in the details, as always. Still, the "short order" aspect should likely be a design requirement. But we're already starting to slip past the "short order" time scale, so I'm hopeful that Chip is well down the design path already for a lot of the features that I just stated could be left out of scaled-down version of the chip (if it weren't for mask costs).
Although I know many of you will have the opposite take, what really causes me a lot of concern is the infrequency of updates coming out of Parallax. For example, it's been almost 40 days since Chip last came down from the "mount" on Christmas day (and thirty-something since his last post, I believe). Yes, I realize that this means that Chip has his nose to the grindstone, and, no, I don't want him distracted by these forums, but it seems to me that some kind of regular update would be good for both the community and Parallax.
As such, I'd like to suggest providing a short update every two weeks on Friday, whether or not specific progress has been made. I think weekly reports is perhaps too frequent (there'd sometimes be little to report and reporting would consume too much time and would become a burden), and monthly is too infrequent (defeats the purpose of having updates (see below)). By "short update," I don't mean detailed reporting, just a quick list of some of the progress made or problems encountered, such that we would have a basic idea of what was going on (yes, perhaps we have that already). Anyway ,I don't want to pressure Parallax to make a decision on that by creating a separate thread. So, I'm doing it here, where this suggestion can easily be lost in the "noise" of the forums and/or ignored (though apologies for the partial thread hi-jack).
The benefit for the community is that it would help us to know how to make future design plans. And the benefit for Parallax is that it could help motivate them to stay on track, even though I realize that they are highly motivated already. But chip designing is an endeavor that takes all the motivation one can get. Now, as to why I apparently think that the community "deserves" updates, it's because we've both provided and been asked to provide suggestions for the P2 and other things (compilers, programming from Chrome books and so on) along the way. Now please don't jump on me for using the word "deserves" (in quotes, to water it down); ultimately, I realize that we don't have an inalienable right to any information from Parallax (it's their business and providing information costs resources) and I know that we are privileged to have received all the openness that we have. You can't find or hope for a more open company! Some probably wish that they were less open. But I think that my suggestion is fully in line with the way Parallax tends to operate (open and generous, though I feel that they are a bit "off their game" lately by "running silent," even though I understand how that could come about and/or any decision to do so (if there was one)).
Anyway, hopefully, we're within days of another juicy update from Chip or Ken about the current state of the design (maybe one was made during this long post (sorry), though I think it's around midnight before a new work week at Parallax).
But back to the thread topic at hand, I'm glad you created this thread, Cluso99/Ray, because, at the very least, it helps to remind us that "time marches on" and, sure, if the currently-proposed design weren't doable or weren't doable in a reasonable timeframe, then, yes, a different design should be considered. But I'm hopeful that it is doable. I think Chip thinks so, along with Parallax. And about my scaled-down mostly digital version above, I presume that such a variant isn't in the cards due to mask costs and so on. But could an FPGA version of it be released for testing purposes if we're still quite a ways out from a more complete FPGA version? However, once again, I'm guessing that it might just make more sense to push forward towards the complete version, as there's hopefully light at the end of the tunnel, rather than pausing to release a scaled-down variant. But if there were to be consideration given to a simplified version of the chip, I would hope that it could conform with the 16/64/512 (and probably HUB 2.0) design features of the currently-proposed one.
Chip has prolly had a holiday in the intervening weeks.
All of my applications work is now ARM + FPGA. Would have really liked to have used the Parallax FPGA board but it is also still MIA and when it does get released will be far too expensive for the capabilities compared to what else is out there. ARM+FPGA+RAM for 1/2 the price??? How can I justify using Parallax just because I like them and want to support their company?.
Sad. I am a big fan of Parallax and Chip.
That "hot" P2 with 96 I/O would have been a killer for industrial process control / CNC applications but alas it was not meant to be.
I still follow, hope and dream... maybe for the next decade's projects...
BTW, there are lots of great ways to get a daily μC fix. It makes the waiting almost painless.
Haha! Yes! There are new squirrels to chase around every corner!!
Why would you say it's never coming? Parallax have successfully launched a new processor design in the past, why couldn't they do it again?
I personally found it's figures limiting. HubRAM was too small, still is in some ways.
The analogue is quite limited for industrial use, mostly analogue I/O is individually isolated. For that you can't use the Prop directly.
8 powerful Cogs didn't fit with the no-interrupts mantra. I'll be gunning for 32 Cogs with any Prop3 ideas, or at least a return of the hardware threads.
But it seems the cost of chip design and manufacture has been growing exponentially since even the early days.
Has Parallax grown, financially, exponentially since the P1 days?
One could speculate that the ever rising cost of the P2 project could bankrupt the company. Or at least cause them to pull the plug before they run out of cash.
I do hope this is not true but it's a worry.
Remember folks, if you want to see a P2 keep buying P1's !
Sure, Parallax have had to relearn much of their ways when it comes to not only designing this thing but dealing with the modern means of contract manufacturing.
Not everything went to plan. A significant redesign occurred that would normally not be in public viewing. That's all happened now. It's full steam ahead right now.
I'll make a prediction: Future designs, Prop3?, will be more iteration like.
Yes Hardware Threads sounded great and appealed to me as a great way to 'fill up' a COG and thus better use resource.
However, I can also see it comes at a non-zero silicon cost, and is another thing for new users to get their head around.