P1V barrel shifter problem

pik33

It seems the barrel shifter (shl, shr instruction) cannot work properly even at 120 MHz (with DE2-115 board). I have random errors when my program does "deep" (28..30 bits) shl/shr. These errors disappeared when I slowed the Propeller to 100 MHz

Can you check this in your projects?

Time to learn how to write these .sdc files....

pik33

It seems this was not barrel shifter, or not only barrel shifter. Maybe something is too slow here:

wire [31:0] sx        = i[im]                    ? {23'b0, i[sh:sl]}
                    : i[sh:sl] == 9'h1F0    ? {16'b0, ptr[27:14], 2'b0}
                    : i[sh:sl] == 9'h1F1    ? cnt
                    : i[sh:sl] == 9'h1F2    ? pin_in
                    : i[sh:sl] == 9'h1F3    ? pinb_in
                    : i[sh:sl] == 9'h1FC    ? phsa[31:0]
                    : i[sh:sl] == 9'h1FD    ? phsb[31:0]
                                            : sy;
    

I registered port b input:

reg[31:0]pinb2;

always @(posedge clk_cog)
  pinb2<=pinb_in;
//...
: i[sh:sl] == 9'h1F3    ? pinb2
//...

It helped somehow but the only working solution was to return to 80 MHz.

Seairth

pik33 wrote: »

It seems this was not barrel shifter, or not only barrel shifter. Maybe something is too slow here:

wire [31:0] sx        = i[im]                    ? {23'b0, i[sh:sl]}
                    : i[sh:sl] == 9'h1F0    ? {16'b0, ptr[27:14], 2'b0}
                    : i[sh:sl] == 9'h1F1    ? cnt
                    : i[sh:sl] == 9'h1F2    ? pin_in
                    : i[sh:sl] == 9'h1F3    ? pinb_in
                    : i[sh:sl] == 9'h1FC    ? phsa[31:0]
                    : i[sh:sl] == 9'h1FD    ? phsb[31:0]
                                            : sy;
    

I registered port b input:

reg[31:0]pinb2;

always @(posedge clk_cog)
  pinb2<=pinb_in;
//...
: i[sh:sl] == 9'h1F3    ? pinb2
//...

It helped somehow but the only working solution was to return to 80 MHz.

Well, by adding the pinb_in, you did make a deeper mux. Maybe that pushed it over a limit. Try the following:

always @(posedge clk_cog)
if (m[1])
    sy <= i[im]                 ? {23'b0, i[sh:sl]}
        : i[sh:sl] == 9'h1F0    ? {16'b0, ptr[27:14], 2'b0}
	: i[sh:sl] == 9'h1F1    ? cnt
                                : ram_q;

wire [31:0] sx      = i[sh:sl] == 9'h1F2    ? pin_in
                    : i[sh:sl] == 9'h1F3    ? pinb_in
                    : i[sh:sl] == 9'h1FC    ? phsa[31:0]
                    : i[sh:sl] == 9'h1FD    ? phsb[31:0]
                                            : sy;

Since "s" is effectively set over two clock cycles, this just attempts to split the mux into two smaller/shallower ones.