P1V over-clocking experiment

rjo__

I have been working on a Nano-P1V variant (4 Cogs). Nice compile time (7 minutes), works excellent at 80MHz.
The only wrinkle is that even at 100Mhz, serial is corrupted.

So, then I went back to the reference design (8-11-14) and tried to over-clock at 100MHz (4/1)... from pik33's thread on the subject...

In top.tdf

variable

	pll				: altpll with (
						pll_type = "enhanced",
						operation_mode = "normal",
						inclk0_input_frequency = 20000,		-- 20000ps = 50MHz
						clk0_multiply_by = 4,
						clk0_divide_by = 1);

And then in the spin file

CON 
_clkmode = xtal1+pll16x
_clkfreq = 100_000_000

same corrupt result with FullDuplexSerial.
?

pik33

Try setting pll divide by 5, multiply by 20. In my current environment I keep this 5 in the divider (I changed this only in my last VGA where I wanted 106.5 MHz)
Then, if it cannot work @ 100 MHz.. try 120.

rjo__

another cup of coffee:)

rjo__

nope... out of time this morning. Will try 120 later.

jac_goudsmit

I think the P1V (as compiled with the original 2014-08-11 code) either runs at 80MHz or thinks that's what it's doing. My project generates serial output just fine at 115200 bps when I set the mode to xtal1+pll16x and _xinfreq to 5MHz.

===Jac

Peter Jakacki

rjo__ wrote: »

I have been working on a Nano-P1V variant (4 Cogs). Nice compile time (7 minutes), works excellent at 80MHz.
The only wrinkle is that even at 100Mhz, serial is corrupted.

same corrupt result with FullDuplexSerial.
?

I am running fine at 3M baud on a 120MHz clocked P1V with my Tachyon system I use clk0_divide = 5 and multiply by 24. FullDuplexSerial has too much jitter and asymmetries especially noticable at higher baud rates.

jmg

Peter Jakacki wrote: »

I am running fine at 3M baud on a 120MHz clocked P1V with my Tachyon system I use clk0_divide = 5 and multiply by 24. FullDuplexSerial has too much jitter and asymmetries especially noticable at higher baud rates.

What is your 'stutter threshold ' - ie at what CLK speed does it start failing tests ?
What does the timing report - IIRC Chip commented a while back about no multi-path settings yet ?