Verilog questions re variable cog ram size

Cluso99

Here is what I have in my cog_ram.v module.
While the use of COGID works for generating VGA, what I have here is always giving the larger cog ram.
Can you see my problem???

module                cog_ram
    #(
    parameter integer COGID = 0        // Receive COGID(0..7) from cog.v/dig.v
       )
(
input                clk,
input                ena,

input                w,
input         [8:0]    a,
input                a9,                // 10bits
input        [31:0]    d,

output reg    [31:0]    q
);

// COG 0 has 4KB, others have usual 2KB
generate
if (cogID == 0)
    begin
        // 1K x 32 ram
        reg [1023:0] [31:0]    r;                // 4KB (10bits)

        always @(posedge clk)
        begin
            if (ena && w)
                r[{a9,a}] <= d;                // 10bits
            if (ena)
                q <= r[{a9,a}];                // 10bits
        end
    end
else                                        // if (COGID != 0)
    begin
        // 512 x 32 ram
        reg [511:0] [31:0]    r;                // 2KB (9bits)

        always @(posedge clk)
        begin
            if (ena && w)
                r[a] <= d;                    // 9bits
            if (ena)
                q <= r[a];                    // 9bits
        end
    end
endgenerate

endmodule

License GPL3

jmg

Cluso99 wrote: »

Can you see my problem???

maybe this ?
Verilog is case-sensitive

Cluso99

No. Think I did that case change later. Didn't fix anyway.
But these are the warnings (multiple of same)
Warning (10222): Verilog HDL Parameter Declaration warning at cog.v(198): Parameter Declaration in module "cog" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List

pmrobert

COGID gets set in dig.v yes? Perhaps it's set value is not visible in cog_ram as cog_ram is another level down, being called from cog.v I believe?

http://quartushelp.altera.com/12.1/mergedProjects/msgs/msgs/wvrfx_veri_param_decl_behaves_as_local.htm

Willy Ekerslyke

Cluso99 wrote: »

Warning (10222): Verilog HDL Parameter Declaration warning at cog.v(198): Parameter Declaration in module "cog" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List

Change the lines in cog.v 198+ to read localparam rather than parameter. That will get rid of the warnings but I doubt it will change the cog ram sizing issue.

Where in Quartus are you seeing that all the cogs end up with 1K ram? What happens if you change the if COGID == 0 to if COGID == 7, or make it if COGID != 0 and swap the if/else parts?

Cluso99

Thanks Robert & Willy,
May not get time today, but I will try if I can.

I now also need to pass the current executing cog down to cog_alu. I will give this a try in my own and see if I can do it.