Interesting you say this. While the IBM PC was in its infancy I was a young engineer working at an IBM facility that still produced "boat anchor technology" (my term at the time for it). Every time I walked through huge buildings full of that stuff I wondered how many months it would be before most of the company collapsed. It actually took many years - I failed to appreciate the inertia involved. Meanwhile, corporate management failed to appreciate the ultimate size of the monster a few employees were nurturing down in Florida.
IBM was lucky to have a huge cash reserve and tons of equipment on long term leases. Even so it was a close thing.
The way to interpret such attitudes is from the market investment and applications. All the big R&D was in much more expensive equipment. And the software to run on the bigger stuff was totally out of the PC's league both in terms requirements and price.
Of course those commentators didn't foresee, nor wanted to look for, such a massive, and required, evolution of the PC platform to what would make it a viable "workstation" and "server" solution. After all, it did take mind bogglingly huge amounts of money to get there. Intel pretty much wiped the deck clear in the process. AMD will be maintained only to prevent anti-competitive charges.
It's the nature of the free market to form monopolies.
Odd view. A little company known as Acorn created there own 32-Bit CPU called the Acorn RISC Machine (ARM), and it was used pretty much only in acorn computers for a long time, later as the computer side went under Acorn realizing that there were already a good number of third parties adapting the ARM split off the CPU into Advanced RISC Machines (maintaining the acronym ARM).
Today there are more ARM CPU's in active use than there are people on the planet (that is NOT an exaggeration), almost all licensed from ARM inc.
So how is it that Intel wiped the board clean?? It seems to me that Acorns spin off company rules the CPU market now. And in the 1990's there was good competition from PowerPC based computers, and POWER Series CPU based computers. From the mid 1980's through the early 1990's there was good competition from computers using the M680x0 series, and the MIPS. Through the 1980's there was significant competition from the 65xxx, Z80, and other similar CPU's.
So I do not think we have to worry about Intel getting a monopoly. Heck they have to license the 64-bit x86 ISA from AMD, and for the Intel XScale ARM CPU they are paying ARM Ltd for licensing. Could you see the modern systems if AMD were to pull the licensing for the 64-Bit ISA on x86 CPU's (ok AMD would likely lose the licensing for the 32-bit side, though it would hurt Intel more).
Of course, the Web did change the rules. The Wintel monoculture had limited control over that, although M$ did dominate for a while. It took Google to blossom and take that control away for anything to really change. So, yeah, Intel wiped the board with ease while the PC ruled. ARM was biding it's time sensibly and not over reaching, it's world was small. Only once the Web, via Google, allowed ARM to blossom did they do so.
All the others were doomed from the start. They never had a chance to compete head on through simple economics. Hell, ARM still doesn't compete head on.
There's no need for ARM to compete head on in what amounts to a dying desktop market dominated by the WinTel duopoly. ARM has the portable and embedded market which is much larger than selling antique processors bolted to a proprietary OS. Even for M$ their cash cow isn't the OS but the Office suite.
I'm kind of guessing that when the micro-computers were in their infancy pretty much everyone could see what was going to happen. Heck the BBC made documentaries about the forth coming revolution way before it happened.
However, if you are making big expensive mainframes and workstations your marketing guys are of course going to say those things are just toys. You can't just turn a big business like that around on a dime and you have to make your current product look good.
davidsaunders,
So how is it that Intel wiped the board clean??
Don't you recall that for a long time pretty much every computer on every desk in every bussiness or home was an wintel box. Apple had fallen by the way side. There was nothing else for the desktop in business and at home. It was a dark age in computing. The PC had indeed wiped away all that huge variety of early personal computers.
Yeah, yeah, there were some Amiga's and such around. Hardly a blip on the radar.
To a large extent that is still true. Apple recovered and are huge. Using Intel of course!
Yes there are billions of ARMs out there. In a different world of use. They are perhaps converging as most of the world realizes it no longer needs Word or such things.
Anyway, I looking forward to all that being overturned by RISC V. There are some big players behind that. Those guys building mobile stuff don't want the hassle of dealing with ARM licenses any more.
Anyway, I looking forward to all that being overturned by RISC V. There are some big players behind that. Those guys building mobile stuff don't want the hassle of dealing with ARM licenses any more.
I think you mentioned before that there are big players behind RISC V but I can't seem to find the list. Where did you find it posted?
A truly open ISA that makes good since is something that I would like to see. We have had DEC PDP-11, MIPS, ARM, and DLX as far as sencible ISA's are concerned, only DLX is open out of those (if I am not mistaken).
.Though ARMv2 is open, do to its age. What is stopping companies from implementing ARMv2 compatible cores? It can be done with true 32-Bit access (only PC gives a 26-bit limit, and most stuff is data not code). Especially with a very simple MMU bolted on?
Guys like Huawei, LG, NEC, Nokia, NVidia, and Samsung could do with an open standard ISA for use in all the phones, TV's and other stuff they make.
Google and Microsoft are probably keen on someone coming up with low power 64 bit processors for their data centres.
Not sure about Oracle's interest. Perhaps it's the possibility of the 128 bit CPU for those huge databases.
So what about Intel? Why are they sponsoring this effort? Surely the RISC V idea is a direct threat? If the world suddenly switched away from x86 that would not be good for them. On the other hand they do actually have their own FABs, so they could apply their processor expertise to their own RISC V implementation and make a nice version of that. Or perhaps if/when they buy Altera a RISC V core for those FPGA's would be great.
ARM of course would lose out big time if RISC V took off. They could also apply their processor and SoC design expertise to the RISC V ISA. Would people licence it? Who knows?
Interestingly the DLX is a design from the University of California, Berkeley. The guy(s) who came up with DLX are involved in RISC V.
Also DLX is the basis of OpenRISC which is as open as can be.
There is another CPU of sorts that is now Open and is very well designed, with in its limits. That is the Propeller P8X32A.
I had largely ignored it until today. Taking a break from coding I decided to look at the sup forum for the Verilog P8X32 . I am quite impressed with it, and with what people are already doing with it.
I can see a near future with a 64 GPIO Propeller 1, possibly with more cores.
I still say that the Propeller 2 should be a Propeller 1 with the Quad access ops for hub ram, more hub ram, 16 cores, a simple instruction pipeline, a higher clock, and all 64 GPIO's (ports A and . Pipeline it to bring the instruction execution to 2 clocks per instruction. Do that and bring the clock to at least 160MHz (80MIPS per COG), and we would have everything we need, even to implement a general purpose computer if we so wished.
Though Chip seems determined to go with the analog I/O's despite what we already know about simple RDAC's and Sigma Delta ADC's (as well as resistor network flash ADC's). We know that we do not need the analog I/O's (OK it can sometimes save pins).
Point is that all of us use a Open source processor, and one that given some simple updates could easily be used for everything up to and including the implementation of a general purpose computer. And I have not seen another CPU that can do everything the Propeller can. Especially true random number generation.
None of us is using an open source processor by using the Propeller. The Verilog that is open sourced is not what the actual Propeller chips are built from. It came later. Hence it is called an "emulation". Not that I think that is quite the right term for it.
Still I guess if anyone wanted to make Prop clones from it it would work well enough.
I still say that the Propeller 2 should be a Propeller 1 with the Quad access ops for hub ram, more hub ram, 16 cores, a simple instruction pipeline, a higher clock, and all 64 GPIO's (ports A and . Pipeline it to bring the instruction execution to 2 clocks per instruction. Do that and bring the clock to at least 160MHz (80MIPS per COG), and we would have everything we need, even to implement a general purpose computer if we so wished.
You have kind of described the Prop2 in its current form. Except for HubExec.
Though Chip seems determined to go with the analog I/O's despite what we already know about simple RDAC's and Sigma Delta ADC's (as well as resistor network flash ADC's). We know that we do not need the analog I/O's (OK it can sometimes save pins).
The analogue stuff hasn't cost much effort on Chips behalf. Beau did most of that - which is now in the hands of a contractor. Although, the ADCs have probably given a strong impetus to head down the "SmartPins" route - which has yet to be done.
Apart from the time it took to start over with the cooler running design, and going by what happened in the P2-HOT design, probably the biggest time sink is HubExec, again.
PS: I'm speculating a lot here. Chip hasn't said anything recently.
Apart from the time it took to start over with the cooler running design, and going by what happened in the P2-HOT design, probably the biggest time sink is HubExec, again.
I wouldn't be unhappy if that got left out of the P2. I still think the best way to use either the P1 or P2 is paired with a more traditional processor like an ARM or maybe a RISC V.
If P2 has some special support for efficient LMM then I suppose HubExec isn't needed. But it really needs a way to efficiently execute large programs from hub RAM. In lieu of efficient hub execution a larger cog RAM would be nice -- maybe around 8Kbytes per cog.
If P2 has some special support for efficient LMM then I suppose HubExec isn't needed. But it really needs a way to efficiently execute large programs from hub RAM. In lieu of efficient hub execution a larger cog RAM would be nice -- maybe around 8Kbytes per cog.
What if you just add some really fast chip-to-chip communications to talk to a separate "application processor" and only run "soft peripherals" on the P2?
Well, there is "large" and that's "bigger than a COG" type large programs, and there is "bigger than the HUB" type of large programs. The latter case seems perfect for the add on CPU case. The former really should be doable with reasonable efficiency. I suppose there is a kind of paged model too, overlays, etc... that would work well without the add on CPU too. With 16 COGS and that fast HUB RAM, maybe that can really pack a punch using a dedicated memory management COG or two.
Personally, I would be just fine with a hardware enhanced LMM. Say it were reliably 50 percent of native COG speed. Great! We would use the Smile out of that. Direct HUBEXEC is great too. In some ways easier, in some ways harder, due to the memory addressing, need for more instructions and modes, etc...
All up to Chip. If he sees a path to HUBEXEC that makes some sense, then it's likely worth it.
I suppose there is a kind of paged model too, overlays, etc... that would work well without the add on CPU too.
Please let's not go back to that. Do we really want retro technology in a brand new chip?
With 16 COGS and that fast HUB RAM, maybe that can really pack a punch using a dedicated memory management COG or two.
This I can go along with. I've wanted to build a Lisp-like language that uses a separate COG for memory management ever since I learned about the Propeller.
I was not talking about paged memory models, banks, and all that fuss! Hate it.
No, I was talking about the case of a program bigger than the HUB, but not so big as to warrant an entirely new CPU running it. That one could be built in pieces and ran within the HUB nicely as needed. So there is a bigger HUB now. (or we presume) That means there is room for some software to manage memory, and make much better use of storage. For modal things, this can work really well, and the programs can be built with a common piece, tested, stored, then unified with a supervisor type program or interface.
Yes, I favor the MMU COG myself. With more COGS online, this seems attractive.
Is there any chance that P2 could dispense with the term "COG" in favor of just calling them "cores"? I think one of the problems with talking about the Propeller with the uninitiated is the different jargon and COG is at the top of the list.
Why? If we have a quad access to hub RAM every 16 clock cycles, with an execution time of 2 cycles per op, then we can already run hub type code at half of the real clock. I think that is better than using something like a HUBEXEC, by a long run.
Why? If we have a quad access to hub RAM every 16 clock cycles, with an execution time of 2 cycles per op, then we can already run hub type code at half of the real clock. I think that is better than using something like a HUBEXEC, by a long run.
Just my point of view.
Wasn't the quad width hub lost with the new "simpler" P2? I thought that was one of the features of P2-hot that caused its demise.
Comments
IBM was lucky to have a huge cash reserve and tons of equipment on long term leases. Even so it was a close thing.
Today there are more ARM CPU's in active use than there are people on the planet (that is NOT an exaggeration), almost all licensed from ARM inc.
So how is it that Intel wiped the board clean?? It seems to me that Acorns spin off company rules the CPU market now. And in the 1990's there was good competition from PowerPC based computers, and POWER Series CPU based computers. From the mid 1980's through the early 1990's there was good competition from computers using the M680x0 series, and the MIPS. Through the 1980's there was significant competition from the 65xxx, Z80, and other similar CPU's.
So I do not think we have to worry about Intel getting a monopoly. Heck they have to license the 64-bit x86 ISA from AMD, and for the Intel XScale ARM CPU they are paying ARM Ltd for licensing. Could you see the modern systems if AMD were to pull the licensing for the 64-Bit ISA on x86 CPU's (ok AMD would likely lose the licensing for the 32-bit side, though it would hurt Intel more).
All the others were doomed from the start. They never had a chance to compete head on through simple economics. Hell, ARM still doesn't compete head on.
It's the Web that saved Apple as well.
However, if you are making big expensive mainframes and workstations your marketing guys are of course going to say those things are just toys. You can't just turn a big business like that around on a dime and you have to make your current product look good.
davidsaunders, Don't you recall that for a long time pretty much every computer on every desk in every bussiness or home was an wintel box. Apple had fallen by the way side. There was nothing else for the desktop in business and at home. It was a dark age in computing. The PC had indeed wiped away all that huge variety of early personal computers.
Yeah, yeah, there were some Amiga's and such around. Hardly a blip on the radar.
To a large extent that is still true. Apple recovered and are huge. Using Intel of course!
Yes there are billions of ARMs out there. In a different world of use. They are perhaps converging as most of the world realizes it no longer needs Word or such things.
Anyway, I looking forward to all that being overturned by RISC V. There are some big players behind that. Those guys building mobile stuff don't want the hassle of dealing with ARM licenses any more.
For sure it was on a Power Point slide at the 1st RISC-V Workshop as seen on video here: https://www.youtube.com/watch?v=A5kpo_ff98M or perhaps one of the other videos from that event https://www.youtube.com/channel/UC5gLmcFuvdGbajs4VL-WU3g
Ha, I put that video on, fell asleep, then woke up to find the list there. Right at the end.
That's 42 mins, 20 secs into https://www.youtube.com/watch?v=A5kpo_ff98M
Anyway, that is a pretty substantial list of heavy weight sponsors. If they are all serious about it, x86 and ARM could be obsolete in short order.
And they all have very good reason to be serious about it.
Interesting presentation. Thanks for posting the link. An open and rational ISA is long overdue.
.Though ARMv2 is open, do to its age. What is stopping companies from implementing ARMv2 compatible cores? It can be done with true 32-Bit access (only PC gives a 26-bit limit, and most stuff is data not code). Especially with a very simple MMU bolted on?
Additionally, MIPS 2 does not have the efficiency and code density RISC V is proposing.
Might as well build on an ISA that does not need a MPU.
Also DLX is the basis of OpenRISC which is as open as can be.
It's probably quite telling that Intel is on the list but ARM is not.
Nice to see Oracle there, I guess that means Sun's team didn't get dismantled.
Guys like Huawei, LG, NEC, Nokia, NVidia, and Samsung could do with an open standard ISA for use in all the phones, TV's and other stuff they make.
Google and Microsoft are probably keen on someone coming up with low power 64 bit processors for their data centres.
Not sure about Oracle's interest. Perhaps it's the possibility of the 128 bit CPU for those huge databases.
So what about Intel? Why are they sponsoring this effort? Surely the RISC V idea is a direct threat? If the world suddenly switched away from x86 that would not be good for them. On the other hand they do actually have their own FABs, so they could apply their processor expertise to their own RISC V implementation and make a nice version of that. Or perhaps if/when they buy Altera a RISC V core for those FPGA's would be great.
ARM of course would lose out big time if RISC V took off. They could also apply their processor and SoC design expertise to the RISC V ISA. Would people licence it? Who knows?
I had largely ignored it until today. Taking a break from coding I decided to look at the sup forum for the Verilog P8X32
I can see a near future with a 64 GPIO Propeller 1, possibly with more cores.
I still say that the Propeller 2 should be a Propeller 1 with the Quad access ops for hub ram, more hub ram, 16 cores, a simple instruction pipeline, a higher clock, and all 64 GPIO's (ports A and
Though Chip seems determined to go with the analog I/O's despite what we already know about simple RDAC's and Sigma Delta ADC's (as well as resistor network flash ADC's). We know that we do not need the analog I/O's (OK it can sometimes save pins).
Point is that all of us use a Open source processor, and one that given some simple updates could easily be used for everything up to and including the implementation of a general purpose computer. And I have not seen another CPU that can do everything the Propeller can. Especially true random number generation.
Still I guess if anyone wanted to make Prop clones from it it would work well enough.
The analogue stuff hasn't cost much effort on Chips behalf. Beau did most of that - which is now in the hands of a contractor. Although, the ADCs have probably given a strong impetus to head down the "SmartPins" route - which has yet to be done.
Apart from the time it took to start over with the cooler running design, and going by what happened in the P2-HOT design, probably the biggest time sink is HubExec, again.
PS: I'm speculating a lot here. Chip hasn't said anything recently.
Personally, I would be just fine with a hardware enhanced LMM. Say it were reliably 50 percent of native COG speed. Great! We would use the Smile out of that. Direct HUBEXEC is great too. In some ways easier, in some ways harder, due to the memory addressing, need for more instructions and modes, etc...
All up to Chip. If he sees a path to HUBEXEC that makes some sense, then it's likely worth it.
No, I was talking about the case of a program bigger than the HUB, but not so big as to warrant an entirely new CPU running it. That one could be built in pieces and ran within the HUB nicely as needed. So there is a bigger HUB now. (or we presume) That means there is room for some software to manage memory, and make much better use of storage. For modal things, this can work really well, and the programs can be built with a common piece, tested, stored, then unified with a supervisor type program or interface.
Yes, I favor the MMU COG myself. With more COGS online, this seems attractive.
Why? If we have a quad access to hub RAM every 16 clock cycles, with an execution time of 2 cycles per op, then we can already run hub type code at half of the real clock. I think that is better than using something like a HUBEXEC, by a long run.
Just my point of view.