I cannot believe that is true. Is it really possible that people are going to write a compiler for an instruction set that does not exist?
It is true although I think it was believed at the time that the P2 instruction set was forthcoming. When it did not arrive as expected, focus was shifted to P1 with the idea that P2 would be done when the P2 instruction set was defined. Eventually, a P2 instruction set and FPGA image were released and PropGCC was ported to that instruction set. As we all know, that instruction set was abandoned early this year. No work has been done to update PropGCC for P2 since then. We're waiting for the new instruction set.
Edit: An possibly interesting side note is that C and C++ code ran on that early version of P2 before Spin code did. In fact, the first Spin code to run on it was translated by spin2cpp. I'm not sure "real" Spin code ever ran on that version of P2.
A P2 spec was posted on the PropGCC developer's forum around July 2011. I recall adding P2 support in spinsim around that time. A public version of the P2 spec was posted on parallaxsemiconductor.com at the end of 2011 or beginning of 2012.
.. Of course, P2 is more important for Parallax than it is for the customers. We can always use some other chip. There are several alternatives available, and more are coming out as time moves on.....
To reflect on the advances of others, I see TI now offers 16b ADCs in their 200MHz Delfino family, up to 1MBF/164kR
This part also mentions Support for 12-Pin 3.3 V-Compatible Universal (eQEP) Modules Parallel Port (uPP) Interface
The uPP is a new feature to the C2000 MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces - sounds similar to the Spansion Hyperbus, also 12p parallel.
Their new TM4C12x series has shiploads of peripherals, and a $20 Launchpad.
This part has Ethernet (MAC+PHY) and HS/FS USB, and CAN, and many timers/uarts/pwm/ADC.
M4 core and 1MB Flash/256K RAM
I think that the new Verilog toy was released precisely to avoid such questions / pressure
We will provide a schedule soon.
The Verilog code will certainly feed the forumistas for a while, but it wasn't released just to take the pressure off of us. But I concur that it's kept you all occupied for a while!
...I concur that it's kept you all occupied for a while!
Speaking only for myself, it certainly has. In fact I've never been more occupied in my entire life. Both P1 and P1V have played important roles in that.
In fact...sleeping is a burden. Thank goodness four hours of that nonsense suffices per day.
I continue to watch this forum.
It is true that the P1V has provided us with a distraction. However, it has been a pleasant distraction and is allowing us to try things rather than keep asking questions of Chip. There are some good ideas coming out of the P1V now and possibly some may make the cut into the P2.
The Verilog code will certainly feed the forumistas for a while, but it wasn't released just to take the pressure off of us. But I concur that it's kept you all occupied for a while!
Ken Gracey
Please please please don't force anything. At the same time please do what you can to restrain the feature creep that I've seen being asked for and get the P2 released as soon as you can! Add all those cool features to the P3 -P4 at a later date!!
As Linus Travolds <sp?> once said "release early, release often". In my never humble opinion it's better to have a reasonable number of versions of a MCU then the one perfect MCU that's never released. In the end I'd rather have 2-5 very similar MCUs that each has it's niche then the "jack of all trade but master of none" that never gets released.
Pick the path you want to follow and make a series of MCUs that follow that path!
Please please please don't force anything. At the same time please do what you can to restrain the feature creep that I've seen being asked for and get the P2 released as soon as you can! Add all those cool features to the P3 -P4 at a later date!!
As Linus Travolds <sp?> once said "release early, release often". In my never humble opinion it's better to have a reasonable number of versions of a MCU then the one perfect MCU that's never released. In the end I'd rather have 2-5 very similar MCUs that each has it's niche then the "jack of all trade but master of none" that never gets released.
Pick the path you want to follow and make a series of MCUs that follow that path!
You got it, 4x5n. I'm behind your thoughts entirely.
4x5n, you're preaching to the choir with a church member who's felt this way since he was baptized. I realize that the path to success is frequent releases with incremental improvements, starting with a constrained specification and schedule to ensure completion. Feature creep is a certain way to derail a project, small or big.
We work with what Chip produces. While I provide lots of influence [noise?] on the inside, where we go and how fast we arrive with this effort is ultimately up to him. I continue to provide an environment where he can effectively do his work, free of anything to worry about in Rocklin.
On behalf of our customers, I'll make a special call to Chip to exercise restraint and get this finished.
As Linus Travolds <sp?> once said "release early, release often". In my never humble opinion it's better to have a reasonable number of versions of a MCU then the one perfect MCU that's never released. In the end I'd rather have 2-5 very similar MCUs that each has it's niche then the "jack of all trade but master of none" that never gets released.
Pick the path you want to follow and make a series of MCUs that follow that path!
While I don't disagree with the get it done sentiment, there is a fundamental difference between software and hardware development cycles. Hardware always has significant outsourced config/testing costs with each design in addition to the setup costs for each production run of each variant. The more production variants there are the more turn-over is needed to support this associated waste.
I sort of agree with you. Chip should have had a P-1.5 out a long time ago(say 2010) to show people that the Prop wasn't just a one-off micro, Instead we have to wait until probably mid 2015 before we see silicon. That's a very long time between new products when you take in when the Propeller was released.in 2006. That's 8 years and is simply too long IMO..
Now the wait doesn't much bother me since there are other choices available and I suspect others that have waited have moved on as well. I'll still use the P-2, if it ever comes out, but it's not a serious focus anymore. It just can't be.
With hardware, we want to stick with "Measure twice, cut once"; rather than "Measure once, cut yourself"
With software, we want to do incremental releases, and regression test EVERYTHING after every change.
Many folks confuse parts of these, making everyone's jobs tougher.
I hope that I nobody got the impression that I think Parallax should release buggy chips or chips with very little differences between them. What is needed is a type of technology freeze. I read posts here that go along the lines of "we need this extra feature" or "Chip could you add this feature because I would like it" (the quotes aren't an indication of actual quotes). The specs for the P2 have been published and a micro needs to be made to as close to those specs as possible. Anything else should be reserved for the P3 and beyond! If design changes continue to be made the P2 will never be made and that's not good for anyone. Make the P2 as it is and as soon as it's released start the work on the P3!
I hope that I nobody got the impression that I think Parallax should release buggy chips or chips with very little differences between them. What is needed is a type of technology freeze. I read posts here that go along the lines of "we need this extra feature" or "Chip could you add this feature because I would like it" (the quotes aren't an indication of actual quotes). The specs for the P2 have been published and a micro needs to be made to as close to those specs as possible. Anything else should be reserved for the P3 and beyond! If design changes continue to be made the P2 will never be made and that's not good for anyone. Make the P2 as it is and as soon as it's released start the work on the P3!
Nah, I don't think that anybody got the impression we should treat chip development like software development. Chip would also agree with your statement - he's ready to be done with this project and move to the next.
I realize that the path to success is frequent releases with incremental improvements, starting with a constrained specification and schedule to ensure completion.
That may be more possible with FPGA + verilog pathways, but notice this includes an implicit specification, and one that revises over time.
It is important to ensure any chip released still has a critical mass of market, (the area under the curve is what matters to a business) and that does change every 6-9 months.
Whilst frequent releases naturally track this effect, less frequent releases still need to factor it in.
That means you cannot quite take a 2011 P2 spec, and 'just ship it' in 2015.
That's bull-**** marketing talk again. While everyone wants pipe-dreams they'll happily take what's available. If Parallax had shipped the cut-down (from the 2011 256kB spec) 128kB version last year, people would still have used it and done some neat stuff.
Why is there no status page for p1.5/2/?? on the parallax website? I am curious, but not enough to wade three different 100 page threads to see where things are at.
For the same reason there is no status update page for development progress of any other micro-controller or other chip made by any other companies.
Often you will not even know what companies are working on until it's released.
We are very honored that Parallax has been so open about P2 developments to the point of inviting input from these very forum members.
What value would such a status page have anyway? A year or so ago the P2 design even got a far as a shuttle run. Such a status page would have indicated it was as good as done and will be shipping very soon.
That shuttle run failed. The design got enhanced and enhanced. Again the status page may have indicated it was nearly done. But that design turned out to be unworkable in practice. Again we are into a redesign.
All these ups and downs are know to anyone interested who follows these threads. A status page would have been woefully wrong for a long time.
Yeah well, look at the pic32mz. Parallax is parallax, and could have a status page or locked/sticky thread for this purpose. This doesn't obligate anyone to produce, and would keep the curious thread starters at bay.
Yeah well, look at the pic32mz. Parallax is parallax, and could have a status page or locked/sticky thread for this purpose. This doesn't obligate anyone to produce, and would keep the curious thread starters at bay.
We will be posting an update next week, on Tuesday or Wednesday at the latest.
We're doing our best to provide frequent updates to you.
If Parallax had shipped the cut-down (from the 2011 256kB spec) 128kB version last year, people would still have used it and done some neat stuff.
That admits there never was a commercially ship-able version. There have been many passes, and the closest one failed power envelope. Since then, nothing has been close to release-able (yet).
There WILL be extensive FPGA tests before any device ships, Parallax is not going to magically "pop out a P2n"
There is still a lot of detail definition and practical code testing to do, especially around the Smart Pins area of P2n.
That will ensure the device does cover real-use cases. Verilog Code will be changed in this phase.
There is no 'spec to ship', the Tested Verilog becomes the spec.
That admits there never was a commercially ship-able version.
Stay on subject. I was answering the always stupid marketing assertion that last year's spec is worthless this year.
I just had a quick peek at the brochure for the Pic32MZ and noted they use Mips for their 32 bit line. Bit of a win for Mips there! Mips had been squished at the top end long ago and Arm did well at keeping Mips out of cellphones. Now they've popped out at the bottom end.
We will be posting an update next week, on Tuesday or Wednesday at the latest.
I'm looking forward to seeing the status update today. It will be nice to get some news on the P2 development since it's been a while since we've heard any details.
Comments
Edit: An possibly interesting side note is that C and C++ code ran on that early version of P2 before Spin code did. In fact, the first Spin code to run on it was translated by spin2cpp. I'm not sure "real" Spin code ever ran on that version of P2.
A P2 spec was posted on the PropGCC developer's forum around July 2011. I recall adding P2 support in spinsim around that time. A public version of the P2 spec was posted on parallaxsemiconductor.com at the end of 2011 or beginning of 2012.
To reflect on the advances of others, I see TI now offers 16b ADCs in their 200MHz Delfino family, up to 1MBF/164kR
This part also mentions
Support for 12-Pin 3.3 V-Compatible Universal (eQEP) Modules Parallel Port (uPP) Interface
The uPP is a new feature to the C2000 MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces
- sounds similar to the Spansion Hyperbus, also 12p parallel.
Their new TM4C12x series has shiploads of peripherals, and a $20 Launchpad.
This part has Ethernet (MAC+PHY) and HS/FS USB, and CAN, and many timers/uarts/pwm/ADC.
M4 core and 1MB Flash/256K RAM
Difficult times to make a new 180nm design near 2015.
Potatohead, Yeah! No worries
We will provide a schedule soon.
The Verilog code will certainly feed the forumistas for a while, but it wasn't released just to take the pressure off of us. But I concur that it's kept you all occupied for a while!
Ken Gracey
I haven't looked at the P2 forum in months. Guess I didn't miss very much.
Speaking only for myself, it certainly has. In fact I've never been more occupied in my entire life. Both P1 and P1V have played important roles in that.
In fact...sleeping is a burden. Thank goodness four hours of that nonsense suffices per day.
It is true that the P1V has provided us with a distraction. However, it has been a pleasant distraction and is allowing us to try things rather than keep asking questions of Chip. There are some good ideas coming out of the P1V now and possibly some may make the cut into the P2.
Please please please don't force anything. At the same time please do what you can to restrain the feature creep that I've seen being asked for and get the P2 released as soon as you can! Add all those cool features to the P3 -P4 at a later date!!
As Linus Travolds <sp?> once said "release early, release often". In my never humble opinion it's better to have a reasonable number of versions of a MCU then the one perfect MCU that's never released. In the end I'd rather have 2-5 very similar MCUs that each has it's niche then the "jack of all trade but master of none" that never gets released.
Pick the path you want to follow and make a series of MCUs that follow that path!
You got it, 4x5n. I'm behind your thoughts entirely.
4x5n, you're preaching to the choir with a church member who's felt this way since he was baptized. I realize that the path to success is frequent releases with incremental improvements, starting with a constrained specification and schedule to ensure completion. Feature creep is a certain way to derail a project, small or big.
We work with what Chip produces. While I provide lots of influence [noise?] on the inside, where we go and how fast we arrive with this effort is ultimately up to him. I continue to provide an environment where he can effectively do his work, free of anything to worry about in Rocklin.
On behalf of our customers, I'll make a special call to Chip to exercise restraint and get this finished.
Ken Gracey
While I don't disagree with the get it done sentiment, there is a fundamental difference between software and hardware development cycles. Hardware always has significant outsourced config/testing costs with each design in addition to the setup costs for each production run of each variant. The more production variants there are the more turn-over is needed to support this associated waste.
Software releases have no such wastage.
With software, we want to do incremental releases, and regression test EVERYTHING after every change.
Many folks confuse parts of these, making everyone's jobs tougher.
I sort of agree with you. Chip should have had a P-1.5 out a long time ago(say 2010) to show people that the Prop wasn't just a one-off micro, Instead we have to wait until probably mid 2015 before we see silicon. That's a very long time between new products when you take in when the Propeller was released.in 2006. That's 8 years and is simply too long IMO..
Now the wait doesn't much bother me since there are other choices available and I suspect others that have waited have moved on as well. I'll still use the P-2, if it ever comes out, but it's not a serious focus anymore. It just can't be.
I hope that I nobody got the impression that I think Parallax should release buggy chips or chips with very little differences between them. What is needed is a type of technology freeze. I read posts here that go along the lines of "we need this extra feature" or "Chip could you add this feature because I would like it" (the quotes aren't an indication of actual quotes). The specs for the P2 have been published and a micro needs to be made to as close to those specs as possible. Anything else should be reserved for the P3 and beyond! If design changes continue to be made the P2 will never be made and that's not good for anyone. Make the P2 as it is and as soon as it's released start the work on the P3!
Nah, I don't think that anybody got the impression we should treat chip development like software development. Chip would also agree with your statement - he's ready to be done with this project and move to the next.
Ken Gracey
That may be more possible with FPGA + verilog pathways, but notice this includes an implicit specification, and one that revises over time.
It is important to ensure any chip released still has a critical mass of market, (the area under the curve is what matters to a business) and that does change every 6-9 months.
Whilst frequent releases naturally track this effect, less frequent releases still need to factor it in.
That means you cannot quite take a 2011 P2 spec, and 'just ship it' in 2015.
You'll need Potatohead's help on this one. :P
Often you will not even know what companies are working on until it's released.
We are very honored that Parallax has been so open about P2 developments to the point of inviting input from these very forum members.
What value would such a status page have anyway? A year or so ago the P2 design even got a far as a shuttle run. Such a status page would have indicated it was as good as done and will be shipping very soon.
That shuttle run failed. The design got enhanced and enhanced. Again the status page may have indicated it was nearly done. But that design turned out to be unworkable in practice. Again we are into a redesign.
All these ups and downs are know to anyone interested who follows these threads. A status page would have been woefully wrong for a long time.
We will be posting an update next week, on Tuesday or Wednesday at the latest.
We're doing our best to provide frequent updates to you.
Ken Gracey
That admits there never was a commercially ship-able version. There have been many passes, and the closest one failed power envelope. Since then, nothing has been close to release-able (yet).
There WILL be extensive FPGA tests before any device ships, Parallax is not going to magically "pop out a P2n"
There is still a lot of detail definition and practical code testing to do, especially around the Smart Pins area of P2n.
That will ensure the device does cover real-use cases. Verilog Code will be changed in this phase.
There is no 'spec to ship', the Tested Verilog becomes the spec.
Stay on subject. I was answering the always stupid marketing assertion that last year's spec is worthless this year.
I just had a quick peek at the brochure for the Pic32MZ and noted they use Mips for their 32 bit line. Bit of a win for Mips there! Mips had been squished at the top end long ago and Arm did well at keeping Mips out of cellphones. Now they've popped out at the bottom end.
take a peek at how many errata they have for the pic32mz... last time I looked I did not like the errata at all...
I'm not going to read all that but I see that only one in the list has been fixed between Rev A3 and Rev A4 silicons.