- Apparently you can send a command to (modern) SD/uSD cards that enables 50Mbps SPI transfers - something that combined with SERDES should allow ~6MB/sec reads
- MMC+ adds 4 and 8 bit modes, dual speeds - up to 26Mhz (x1,x4,x8) and 52Mhz (x1,x4,x8) modes, and from my research is license fee free (x8 modes need 13 pin cards/sockets)
Only problem is MMC+ cards are hard to find. But x4 @ 52Mhz is 26MB/sec... also research suggests it is compatible with SD 4-bit mode, so apparently MMC+ specs could be used for SD...
BUT: SD is still trade secret / patent encumbered, so theoretically they could still go after 4 bit SD usage
IDE/SATA/CF:
- I like IDE/CF, but hate the loss of pins. For fastest interface, the minimum I think is around 22 pins, or about 15 pins for 8 bit bus and loss of 1/2 capacity of the drive
- SATA/IDE chips are common, but still use a ton of pins
BUT: SD is still trade secret / patent encumbered, so theoretically they could still go after 4 bit SD usage
Quad SPI FLASH, and even DDR Quad SPI memory chips are readily available, so that is a good upper target.
Supporting those has no risk, and if it happens to also work on SD, that is a by-product.
I don't see the need, but have fun doing this. Why not?
Do keep in mind you will lose a lot of p2 pins for the external ram. That and ide... you wont leave hardly any pins left. Yes you could do it with the internal 126k, but what is the point of that much storage for such a tiny system and memory size.
It should be possible to share the 16 databus pins and the 3 adress pins between the SDRAM and the IDE/ATA interface, so you need only a few additional pins.
But on the Prop2 module from Parallax the pins that go to the SDRAM will not be easy accessible, I think.
Using a IDE to SATA chip should not be difficult, but even getting running with plain IDE would be great for now. Don't worry about the lack of pins we can sort that out later.
Are there specific areas you need assistance with? It seems like you have a good handle on it
In the case of the simultaneous use of the interconnections between the Propeller, the Ram and IDE interface, due to the switching speed and the possibility of crostalk between signals due to the presence of the flat cable and associated connectors, that even in version 80-way interleaved grounding, will introduce distortions in waveforms.
IMHO, in cases like this, the addition of transceivers and their control lines would become mandatory, although some of them may be shared in creative ways.
Ozpropdev said that DE0-nano only have 28 pins available. So we have 26 left for IDE signals.
IDE has two modes of operation: 8 bit data width and 16 bit data width. I strongly recommend that we should use 16 bits, so we don't have any performance penalty. 16 bit mode is also the normal mode of operation.
In that case we will have 10 pins left for control signals
How many control signals we will use from IDE? Two options:
- we can save one pin or two if we don't use DMA.
- use all control signals (some people will want also to use the add-on board directly on DE0-nano for custom verilog code with DMA).
Also, the old standards say that signals are driven at 5V. Currently it will be easier to use directly 3.3v. How? Using compact flash. CF can be attached to IDE port with a mode called "True IDE Mode". I think this is the easiest way to have a cheap, portable and easy to interface drive.
Looking at the pin configuration of the FPGA for DE0 it looks like there's 29 pins available, not 28 as I stated earlier.
This does not include the Rx and Tx pins. The 4 eeprom pins may be usable as well?
The PDF of the DE0 add-on board has all the pins shown, it might be a good starting point.
In total there are 32 34 pins
P0..25 are available without limit GPIO
P26..27 look like input only (adjacent P0 and P1)
P86..89 shared with the flash boot memory (up to 3 of those signals may toggle during startup)
P90..91 for serial rx, tx to the PC
All these pins are on the same 40 pin header. There are a couple of pins adjacent to the P0 and P1 pins that I think are inaccessible, but I haven't checked for sure. And there are two pins from the DAC that I don't think we can access simply.
edit: I think these are P26 and P27 (input only). Need to check this. I know they don't work as outputs.
So, yes it would be good to pick the 10 (12?) most useful control signals, and more optional ones that may interfere with the SPI flash memory if installed. There seem to be 15 or so control signals total?
IOREADY (pin 27) Used by the drive to slow down the host (can be omitted)
CSEL (pin 28) Used only if you need to attach 2 drives.
PDIAG (pin 34) Used only if you need to attach 2 drives. (Also for UDMA)
IOCS16- (pin 32) Only used on PIO modes 0,1 and 2 (can be omitted)
DASP (pin 39) Used for activity LED (Open collector)
Comments
- Apparently you can send a command to (modern) SD/uSD cards that enables 50Mbps SPI transfers - something that combined with SERDES should allow ~6MB/sec reads
- MMC+ adds 4 and 8 bit modes, dual speeds - up to 26Mhz (x1,x4,x8) and 52Mhz (x1,x4,x8) modes, and from my research is license fee free (x8 modes need 13 pin cards/sockets)
Only problem is MMC+ cards are hard to find. But x4 @ 52Mhz is 26MB/sec... also research suggests it is compatible with SD 4-bit mode, so apparently MMC+ specs could be used for SD...
BUT: SD is still trade secret / patent encumbered, so theoretically they could still go after 4 bit SD usage
IDE/SATA/CF:
- I like IDE/CF, but hate the loss of pins. For fastest interface, the minimum I think is around 22 pins, or about 15 pins for 8 bit bus and loss of 1/2 capacity of the drive
- SATA/IDE chips are common, but still use a ton of pins
Quad SPI FLASH, and even DDR Quad SPI memory chips are readily available, so that is a good upper target.
Supporting those has no risk, and if it happens to also work on SD, that is a by-product.
Depending on how fast SerDes finally delivers, perhaps a header/bridge board with
QuadSPI -> CPLD -> IDE connector ?
Do keep in mind you will lose a lot of p2 pins for the external ram. That and ide... you wont leave hardly any pins left. Yes you could do it with the internal 126k, but what is the point of that much storage for such a tiny system and memory size.
But on the Prop2 module from Parallax the pins that go to the SDRAM will not be easy accessible, I think.
Andy
Using a IDE to SATA chip should not be difficult, but even getting running with plain IDE would be great for now. Don't worry about the lack of pins we can sort that out later.
Are there specific areas you need assistance with? It seems like you have a good handle on it
IMHO, in cases like this, the addition of transceivers and their control lines would become mandatory, although some of them may be shared in creative ways.
Yanomani
Tubular, Thanks. Yes, I need help to identify which signals from IDE interface we are going to use. And which pins of P2 (de0-nano) we will use.
The idea is to control P2 with just only two RS232 pins all other pins will be available to IDE.
RS232 (2 pins) <-> (2 pins) P2 (de0-nano) <-> (? pins) IDE/ATA
Ozpropdev said that DE0-nano only have 28 pins available. So we have 26 left for IDE signals.
IDE has two modes of operation: 8 bit data width and 16 bit data width. I strongly recommend that we should use 16 bits, so we don't have any performance penalty. 16 bit mode is also the normal mode of operation.
In that case we will have 10 pins left for control signals
How many control signals we will use from IDE? Two options:
- we can save one pin or two if we don't use DMA.
- use all control signals (some people will want also to use the add-on board directly on DE0-nano for custom verilog code with DMA).
Also, the old standards say that signals are driven at 5V. Currently it will be easier to use directly 3.3v. How? Using compact flash. CF can be attached to IDE port with a mode called "True IDE Mode". I think this is the easiest way to have a cheap, portable and easy to interface drive.
So I think we can start discussing this first.
Looking at the pin configuration of the FPGA for DE0 it looks like there's 29 pins available, not 28 as I stated earlier.
This does not include the Rx and Tx pins. The 4 eeprom pins may be usable as well?
The PDF of the DE0 add-on board has all the pins shown, it might be a good starting point.
P0..25 are available without limit GPIO
P26..27 look like input only (adjacent P0 and P1)
P86..89 shared with the flash boot memory (up to 3 of those signals may toggle during startup)
P90..91 for serial rx, tx to the PC
All these pins are on the same 40 pin header. There are a couple of pins adjacent to the P0 and P1 pins that I think are inaccessible, but I haven't checked for sure. And there are two pins from the DAC that I don't think we can access simply.
edit: I think these are P26 and P27 (input only). Need to check this. I know they don't work as outputs.
So, yes it would be good to pick the 10 (12?) most useful control signals, and more optional ones that may interfere with the SPI flash memory if installed. There seem to be 15 or so control signals total?
Without DMA: 24 pins. All of them are P2 outputs, but D[0..15] are also inputs (bidirectional IO).
A0, A1, A2
CS0, CS1 (**) Some people tie CS0 and CS1 to "0" and "1". So, they can use just 22 pins.
RD-, WR-
D[0..15] (Bidirectional, I&O)
With DMA: 27 pins. Same as above plus:
DMARQ (P2 Input)
IRQ (P2 Input)
GND (pins 2,19,22,24,26,30,40)
Other signals (don't need to be connected to P2):
CSEL (pin 28) Used only if you need to attach 2 drives.
PDIAG (pin 34) Used only if you need to attach 2 drives. (Also for UDMA)
IOCS16- (pin 32) Only used on PIO modes 0,1 and 2 (can be omitted)
DASP (pin 39) Used for activity LED (Open collector)