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Add-on card for IDE Drive to P2 DE0-nano. Any interest? — Parallax Forums

Add-on card for IDE Drive to P2 DE0-nano. Any interest?

RamonRamon Posts: 484
edited 2013-11-08 08:45 in Propeller 2
Hi All,

There has been a few threads about attaching a Propeller (1) to IDE drive:

"Prop + IDE drives?" : http://forums.parallax.com/showthread.php/100805-Prop-IDE-drives
"Propeller hooked up to a hard drive" : http://forums.parallax.com/showthread.php/98568-Propeller-hooked-up-to-a-hard-drive

There is also documentation of succesfull projects for other micros:

http://www.pjrc.com/tech/8051/ide/wesley.html
http://www.telegraphics.com.au/sw/info/picide.html
http://www.retroleum.co.uk/ide_interface.html

A friend recently lend me a DE0-nano.

As there are several of you that also have the FPGA, is there interest to work together to make a IDE add-on board PCB and also software driver for P2?
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Comments

  • Heater.Heater. Posts: 21,230
    edited 2013-11-04 00:51
    Not really.

    It would use lot's of pins, be slow and expensive. I'm not sure what it gets you that an SD card cannot.
  • RamonRamon Posts: 484
    edited 2013-11-04 03:08
    Around 25 pins. Maybe a problem for P1, but P2 has 96 I/O pins, right?

    Slow? Is 25MB/s (PIO 6) slow for you? How many MB/s can you get currently with SD? Is there a royalty free driver for high-speed SD access?

    (I suppose you already know : http://forums.parallax.com/showthread.php/129698-SDCARD-in-4-bit-mode )
  • Heater.Heater. Posts: 21,230
    edited 2013-11-04 07:51
    OK, we have pins to burn on the PII. And speed is good too if you achieve it via bit banging.

    At 25MB/ second you can read or write the entire Props II's RAM in about 5ms. Then what?

    To be of use the Prop would have to be sucking in or blowing out data on some other interface at that speed. What do you have in mind?
  • potatoheadpotatohead Posts: 10,261
    edited 2013-11-04 09:40
    A prop DVD player?
  • ozpropdevozpropdev Posts: 2,792
    edited 2013-11-04 16:20
    These transfer rates look impressive but would be lost on a DE0 board.
    I think the limiting factor here is the DE0-nano itself.
    While the P2 will have 96 I/O pins, the DE0 has only 28 pins.
    This in combination with 1 Cog and 32k Hub ram also makes it difficult.
    Multi-threading wouldn't help here either.
  • RamonRamon Posts: 484
    edited 2013-11-04 21:10
    We just only need 25 pins (IDE) + 2 pins (RS232). I think that 28 pins are enough.

    Just only 512 bytes of RAM are needed to buffer one sector and do simple write/read between RS232 <-> RAM <-> IDE.

    ** DE0-nano is just the tool to make development ready when we have the actual P2 IC. **

    This project will bring HUGE and FAST storage to propeller. It will open the door not only to IDE drives, but also to Compact Flash (in True IDE mode), and CDROM/DVD. There are even ICs that combine NAND flash + integrated IDE controller in LBGA package (and industrial temperature range).
  • pedwardpedward Posts: 1,642
    edited 2013-11-04 21:39
    Spend the effort to make a SATA interface, PATA is going the way of the dodo. With sata you need 4 pins. You also vastly underestimate the amount of code required to drive this. 512 bytes is the least of your troubles.
  • RamonRamon Posts: 484
    edited 2013-11-05 02:53
    Seriously, can P2 handle 1.5Gbps LVDS? If you want SATA, I think you should wait for P3 (with LVDS, NRZ, SERDES, 8b/10b, CRC, and scrambling functions).

    Pedward, with all due respect I think that you understimate the survival capability of ATA (and also what ATA can offer to P2, right now).

    One of SATA 1.0a specification goals was "completely SW transparent w/ ATA (easy transition)" (page 11). "The host interacts ... through a register interface that is equivalent to that presented by a traditional parallel ATA host" (page 25). So any software work done for Parallel ATA could work in SATA (in case someday we get a P3 in our hands, and Hard Disk manufacturers does not remove legacy mode).

    I think that I have some knowlegde of what I am talking about. Several years ago (maybe 8, or 10?), I write some asm code for intel 386 and ms-dos. I was able to read/write and send special commands (SLEEP, Identify ...) both to HD and CD-ROM. (see buggy and awfully commented code attached).

    OK. No one interested, no problem.
  • SapiehaSapieha Posts: 2,964
    edited 2013-11-05 04:17
    Hi Ramon.

    It look interesting.

    Sorry I don't participate from start -- have some health problems.
    My idea I had -- Made some converter that convert AT to I2C else SPI for use with Propellers
    Ramon wrote: »
    Seriously, can P2 handle 1.5Gbps LVDS? If you want SATA, I think you should wait for P3 (with LVDS, NRZ, SERDES, 8b/10b, CRC, and scrambling functions).

    Pedward, with all due respect I think that you understimate the survival capability of ATA (and also what ATA can offer to P2, right now).

    One of SATA 1.0a specification goals was "completely SW transparent w/ ATA (easy transition)" (page 11). "The host interacts ... through a register interface that is equivalent to that presented by a traditional parallel ATA host" (page 25). So any software work done for Parallel ATA could work in SATA (in case someday we get a P3 in our hands, and Hard Disk manufacturers does not remove legacy mode).

    I think that I have some knowlegde of what I am talking about. Several years ago (maybe 8, or 10?), I write some asm code for intel 386 and ms-dos. I was able to read/write and send special commands (SLEEP, Identify ...) both to HD and CD-ROM. (see buggy and awfully commented code attached).

    OK. No one interested, no problem.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-11-05 06:43
    SPI is a good idea for this....
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 07:29
    SPI is a good idea for this....
    Ummm... Doesn't this defeat the purpose of interfacing an IDE drive? Wouldn't using SPI reduce its speed to about the same as an SD card?
  • SapiehaSapieha Posts: 2,964
    edited 2013-11-05 07:47
    Hi David.

    If we use Fast SPI -- That can function

    David Betz wrote: »
    Ummm... Doesn't this defeat the purpose of interfacing an IDE drive? Wouldn't using SPI reduce its speed to about the same as an SD card?
  • RamonRamon Posts: 484
    edited 2013-11-05 08:04
    Sapieha wrote: »
    My idea I had -- Made some converter that convert AT to I2C else SPI for use with Propellers

    Hi Sapieha, (I hope you'll get well soon)

    I had a similar idea as you. To reduce the pin count required by ATA. I thought that some kind of ATA controller/translator to a 8 bit bidirectional data + 2 or 3 control lines. And inmediatly though that something similar to ULPI was perfect. Take a look to http://www.ulpi.org/ . It uses 12 lines (8 bidirectional data + CLK + DIR + NEXT + STOP). Simple, elegant, brilliant.

    As David noticed, if we reduce to much the number of pins, we need to raise clock frequency. We can also do nibble transfer : 4 data bits + 4 control lines, but in this case control lines overhead is 50%. So I think that 12 pins (8 data + 4 control) is a good compromise.

    Initially I wanted to use a CPLD or FPGA to do that (using Lattice MachXO2 or XP2).

    Why Lattice? Because they already have 2 reference designs with Verilog code:

    "RD1040" CompactFlash Controller
    "RD1095" IDE/ATA Interface Controller with WISHBONE

    And also because they have two cheap development boards with 2x20 pin headers easy to attach to IDE interface with little wiring and components. They also have a lot of packaging options, and their JTAG is just a cheap FTDI FT2232.

    There is also a verilog controller on opencores made by Richard Herveille on 2001 (OCIDEC - OpenCores IDE Controller). So there is plenty of information to start making a IDE <-> I2C/SPI translator in Verilog.

    But then Chip made available the P2 for DE0-nano. So I changed my mind. Instead of lattice, if we make an add-on board for DE0-nano, we can use the board not only to make a pure Verilog translator, but we can also make an interface and driver for P2.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 08:50
    Sapieha wrote: »
    Hi David.

    If we use Fast SPI -- That can function
    Yes but we could also use Fast SPI to speed up SD card access as well.
  • SapiehaSapieha Posts: 2,964
    edited 2013-11-05 09:02
    Hi David..

    Yes --- BUT

    Not all of them support that mode


    David Betz wrote: »
    Yes but we could also use Fast SPI to speed up SD card access as well.
  • potatoheadpotatohead Posts: 10,261
    edited 2013-11-05 09:10
    So use the ones that do.
  • SapiehaSapieha Posts: 2,964
    edited 2013-11-05 09:14
    Hi potatohead..

    If You can find that ones that support 20MBit's and more.

    We can test
    potatohead wrote: »
    So use the ones that do.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 09:21
    Sapieha wrote: »
    Hi potatohead..

    If You can find that ones that support 20MBit's and more.

    We can test
    Isn't a class 10 card supposed to be able to transfer 10MB/sec? That's 10 megabytes right, not 10 megabits.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-11-05 09:27
    Unfortunately it also needs the 4 bit mode, with four CRC's ... and even more unfortunately, the 4 bit mode is still patent encumbered (last i heard, and not the CRC part)
    David Betz wrote: »
    Isn't a class 10 card supposed to be able to transfer 10MB/sec? That's 10 megabytes right, not 10 megabits.
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 09:29
    Unfortunately it also needs the 4 bit mode, with four CRC's ... and even more unfortunately, the 4 bit mode is still patent encumbered (last i heard, and not the CRC part)
    How fast can the SPI interface to an SD card go?
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-11-05 09:32
    I believe the SD spec says max 25Mbits.

    The good news is that there are a lot of 8 pin flash chips that support 104Mhz SPI mode, and 25Mhz QSPI mode.

    With the SERDES being discussed, 80Mbits/sec should be possible to the SPI flash when running at 160Mhz, which is not bad at all.
    David Betz wrote: »
    How fast can the SPI interface to an SD card go?
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 09:35
    I believe the SD spec says max 25Mbits.

    The good news is that there are a lot of 8 pin flash chips that support 104Mhz SPI mode, and 25Mhz QSPI mode.
    Thanks. I guess I'm having a hard time understanding how an IDE drive interfaced through SPI could be any faster than an SD card interfaced through SPI. What is "Fast SPI"? Is this a newer SPI interface technology? I tried googling it and all I found were fast SPI libraries for the Arduino.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-11-05 09:38
    An IDE-SPI interface could be made to run at 50Mbits-80Mbits using 4 pins (or only one if CLK/MOSI/MISO are shared with the boot flash), compared to the maximum 25Mbits to the SD card.

    But I think the likelier usage case is LOTS of cheap storage.

    It would be possible to make a 16 bit wide + ~6-8 control signals interface, as posted earlier in this thread, but that's a lot of pins.
    David Betz wrote: »
    Thanks. I guess I'm having a hard time understanding how an IDE drive interfaced through SPI could be any faster than an SD card interfaced through SPI. What is "Fast SPI"? Is this a newer SPI interface technology? I tried googling it and all I found were fast SPI libraries for the Arduino.
  • potatoheadpotatohead Posts: 10,261
    edited 2013-11-05 09:43
    How is the patent licensed? Can ordinary people and small companies get one?

    I'm much more interested in fast electronic storage than I am IDE.

    That said, IDE might be interesting for doing low level disk tricks...
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-05 09:49
    But I think the likelier usage case is LOTS of cheap storage.
    Can't argue with that I guess. However, if you're not going to do a native P2-IDE interface why not make the SPI adapter talk to a SATA drive? Are IDE drives even going to be available much longer?
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-11-05 10:00
    I was considering that, but the controller chips have PCI / PCIe as the host interface, which needs many I/O or an FPGA to drive.

    For my P2 boards, I intend to use uSD and SPI/QSPI for the moment - few pins, inexpensive.

    Sapieha has been wanting to do an IDE-SPI for a few years now, so sooner or later there will be a Mikronauts board to do that :)

    IDE drives should be available for quite a few years yet.
    David Betz wrote: »
    Can't argue with that I guess. However, if you're not going to do a native P2-IDE interface why not make the SPI adapter talk to a SATA drive? Are IDE drives even going to be available much longer?
  • RamonRamon Posts: 484
    edited 2013-11-05 23:59
    potatohead wrote: »
    How is the patent licensed? Can ordinary people and small companies get one?

    https://www.sdcard.org/join/faq/

    Licensing:
    - Update coming soon :) How funny

    Membership:
    - Executive membership level is $4500 per year.
    - General members may attend all meetings and receive all publications. $2000 per year.

    I asked once (to one big partner company of a big FPGA manufacturer) how much for a SD Host License (both netlist and source code). The answer (for both) was "X" followed by 4 zeros (USD).

    You can ask directly to Ken or Chip if they are willing to make SDHC into P2. I think this was discussed before and the answer was: no.
    potatohead wrote: »
    I'm much more interested in fast electronic storage than I am IDE.

    People has the wrong concept to associate IDE/ATA to a 30 years old 3.5" 40Mb seagate drive.

    Actually ATA is the only option for cheap, fast and huge electronic storage. ATA has been also adopted by Compact Flash, SATA !, CD/DVD, and also some specialized ICs in BGA package. Also there are plenty of manufacturers of ATA-CF, ATA-SATA, ATA-USB, ATA-Nand Flash, ATA-Nor Flash adapter ICs for $1 ....

    Why? because there is no need to pay any license or royalty.
  • RamonRamon Posts: 484
    edited 2013-11-06 00:33
    David Betz wrote: »
    if you're not going to do a native P2-IDE interface why not make the SPI adapter talk to a SATA drive?

    Because there is no current cheap CPLD/FPGA with 1.5Gbps LVDS. They are expensive or have more than 300 pins.

    (Maybe Lattice MachXO3 could be used. But it is not available yet. They announced a early access program on October but has not been realized yet)
    David Betz wrote: »
    Are IDE drives even going to be available much longer?

    Yes. Even if that happens, there are a lot of SATA-IDE and CF-IDE adapters for less than US$3.

    (Compare $3 USD to the cost of a FPGA capable of handling SATA signal and protocol)
  • David BetzDavid Betz Posts: 14,516
    edited 2013-11-06 03:52
    Ramon wrote: »
    Because there is no current cheap CPLD/FPGA with 1.5Gbps LVDS. They are expensive or have more than 300 pins.

    (Maybe Lattice MachXO3 could be used. But it is not available yet. They announced a early access program on October but has not been realized yet)



    Yes. Even if that happens, there are a lot of SATA-IDE and CF-IDE adapters for less than US$3.

    (Compare $3 USD to the cost of a FPGA capable of handling SATA signal and protocol)
    Okay, you've convinced me. :-)
    It sounds like an IDE drive interface would be useful for people who need more speed than you can get with an SD card or more capacity. I don't personally need either of those but I imagine some do.
  • potatoheadpotatohead Posts: 10,261
    edited 2013-11-06 06:05
    @Ramon: Ok then. I had no idea IDE was being used in that way and for those reasons!
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