Add-on card for IDE Drive to P2 DE0-nano. Any interest?
Ramon
Posts: 484
Hi All,
There has been a few threads about attaching a Propeller (1) to IDE drive:
"Prop + IDE drives?" : http://forums.parallax.com/showthread.php/100805-Prop-IDE-drives
"Propeller hooked up to a hard drive" : http://forums.parallax.com/showthread.php/98568-Propeller-hooked-up-to-a-hard-drive
There is also documentation of succesfull projects for other micros:
http://www.pjrc.com/tech/8051/ide/wesley.html
http://www.telegraphics.com.au/sw/info/picide.html
http://www.retroleum.co.uk/ide_interface.html
A friend recently lend me a DE0-nano.
As there are several of you that also have the FPGA, is there interest to work together to make a IDE add-on board PCB and also software driver for P2?
There has been a few threads about attaching a Propeller (1) to IDE drive:
"Prop + IDE drives?" : http://forums.parallax.com/showthread.php/100805-Prop-IDE-drives
"Propeller hooked up to a hard drive" : http://forums.parallax.com/showthread.php/98568-Propeller-hooked-up-to-a-hard-drive
There is also documentation of succesfull projects for other micros:
http://www.pjrc.com/tech/8051/ide/wesley.html
http://www.telegraphics.com.au/sw/info/picide.html
http://www.retroleum.co.uk/ide_interface.html
A friend recently lend me a DE0-nano.
As there are several of you that also have the FPGA, is there interest to work together to make a IDE add-on board PCB and also software driver for P2?
Comments
It would use lot's of pins, be slow and expensive. I'm not sure what it gets you that an SD card cannot.
Slow? Is 25MB/s (PIO 6) slow for you? How many MB/s can you get currently with SD? Is there a royalty free driver for high-speed SD access?
(I suppose you already know : http://forums.parallax.com/showthread.php/129698-SDCARD-in-4-bit-mode )
At 25MB/ second you can read or write the entire Props II's RAM in about 5ms. Then what?
To be of use the Prop would have to be sucking in or blowing out data on some other interface at that speed. What do you have in mind?
I think the limiting factor here is the DE0-nano itself.
While the P2 will have 96 I/O pins, the DE0 has only 28 pins.
This in combination with 1 Cog and 32k Hub ram also makes it difficult.
Multi-threading wouldn't help here either.
Just only 512 bytes of RAM are needed to buffer one sector and do simple write/read between RS232 <-> RAM <-> IDE.
** DE0-nano is just the tool to make development ready when we have the actual P2 IC. **
This project will bring HUGE and FAST storage to propeller. It will open the door not only to IDE drives, but also to Compact Flash (in True IDE mode), and CDROM/DVD. There are even ICs that combine NAND flash + integrated IDE controller in LBGA package (and industrial temperature range).
Pedward, with all due respect I think that you understimate the survival capability of ATA (and also what ATA can offer to P2, right now).
One of SATA 1.0a specification goals was "completely SW transparent w/ ATA (easy transition)" (page 11). "The host interacts ... through a register interface that is equivalent to that presented by a traditional parallel ATA host" (page 25). So any software work done for Parallel ATA could work in SATA (in case someday we get a P3 in our hands, and Hard Disk manufacturers does not remove legacy mode).
I think that I have some knowlegde of what I am talking about. Several years ago (maybe 8, or 10?), I write some asm code for intel 386 and ms-dos. I was able to read/write and send special commands (SLEEP, Identify ...) both to HD and CD-ROM. (see buggy and awfully commented code attached).
OK. No one interested, no problem.
It look interesting.
Sorry I don't participate from start -- have some health problems.
My idea I had -- Made some converter that convert AT to I2C else SPI for use with Propellers
If we use Fast SPI -- That can function
Hi Sapieha, (I hope you'll get well soon)
I had a similar idea as you. To reduce the pin count required by ATA. I thought that some kind of ATA controller/translator to a 8 bit bidirectional data + 2 or 3 control lines. And inmediatly though that something similar to ULPI was perfect. Take a look to http://www.ulpi.org/ . It uses 12 lines (8 bidirectional data + CLK + DIR + NEXT + STOP). Simple, elegant, brilliant.
As David noticed, if we reduce to much the number of pins, we need to raise clock frequency. We can also do nibble transfer : 4 data bits + 4 control lines, but in this case control lines overhead is 50%. So I think that 12 pins (8 data + 4 control) is a good compromise.
Initially I wanted to use a CPLD or FPGA to do that (using Lattice MachXO2 or XP2).
Why Lattice? Because they already have 2 reference designs with Verilog code:
"RD1040" CompactFlash Controller
"RD1095" IDE/ATA Interface Controller with WISHBONE
And also because they have two cheap development boards with 2x20 pin headers easy to attach to IDE interface with little wiring and components. They also have a lot of packaging options, and their JTAG is just a cheap FTDI FT2232.
There is also a verilog controller on opencores made by Richard Herveille on 2001 (OCIDEC - OpenCores IDE Controller). So there is plenty of information to start making a IDE <-> I2C/SPI translator in Verilog.
But then Chip made available the P2 for DE0-nano. So I changed my mind. Instead of lattice, if we make an add-on board for DE0-nano, we can use the board not only to make a pure Verilog translator, but we can also make an interface and driver for P2.
Yes --- BUT
Not all of them support that mode
If You can find that ones that support 20MBit's and more.
We can test
The good news is that there are a lot of 8 pin flash chips that support 104Mhz SPI mode, and 25Mhz QSPI mode.
With the SERDES being discussed, 80Mbits/sec should be possible to the SPI flash when running at 160Mhz, which is not bad at all.
But I think the likelier usage case is LOTS of cheap storage.
It would be possible to make a 16 bit wide + ~6-8 control signals interface, as posted earlier in this thread, but that's a lot of pins.
I'm much more interested in fast electronic storage than I am IDE.
That said, IDE might be interesting for doing low level disk tricks...
For my P2 boards, I intend to use uSD and SPI/QSPI for the moment - few pins, inexpensive.
Sapieha has been wanting to do an IDE-SPI for a few years now, so sooner or later there will be a Mikronauts board to do that
IDE drives should be available for quite a few years yet.
https://www.sdcard.org/join/faq/
Licensing:
- Update coming soon
Membership:
- Executive membership level is $4500 per year.
- General members may attend all meetings and receive all publications. $2000 per year.
I asked once (to one big partner company of a big FPGA manufacturer) how much for a SD Host License (both netlist and source code). The answer (for both) was "X" followed by 4 zeros (USD).
You can ask directly to Ken or Chip if they are willing to make SDHC into P2. I think this was discussed before and the answer was: no.
People has the wrong concept to associate IDE/ATA to a 30 years old 3.5" 40Mb seagate drive.
Actually ATA is the only option for cheap, fast and huge electronic storage. ATA has been also adopted by Compact Flash, SATA !, CD/DVD, and also some specialized ICs in BGA package. Also there are plenty of manufacturers of ATA-CF, ATA-SATA, ATA-USB, ATA-Nand Flash, ATA-Nor Flash adapter ICs for $1 ....
Why? because there is no need to pay any license or royalty.
Because there is no current cheap CPLD/FPGA with 1.5Gbps LVDS. They are expensive or have more than 300 pins.
(Maybe Lattice MachXO3 could be used. But it is not available yet. They announced a early access program on October but has not been realized yet)
Yes. Even if that happens, there are a lot of SATA-IDE and CF-IDE adapters for less than US$3.
(Compare $3 USD to the cost of a FPGA capable of handling SATA signal and protocol)
It sounds like an IDE drive interface would be useful for people who need more speed than you can get with an SD card or more capacity. I don't personally need either of those but I imagine some do.