Wow!
I never imagined that the idea of +3 cogs would create so much debate.
The last thing I would ever want to do is waste Chip's time. It was an idea I just put out there.
Yes, we all want silicon but in reality we know that's a little way off. So in the meantime time we continue development.
I see no reason to plan a whole major project on silicon that is not realized yet so why is it necessary to get an 8 cog variant out? Not rhetorical, is there a real need that people see there?
Doesn't the description of this forum read as follows:
Primary purpose is for early adopters of Propeller 2 who run the core in FPGAs, for the creation of programming tools, and for documentation development
In the end this early development helps Parallax when they finally have silicon.
Lots of tools and examples,tutorials etc...
We all win
We could beg Terasic for making a 'DE nano' with Cyclone V E 301Kgates:
Current prices at Digikey and Altera for : stocked & cheapest Cyclone IV or V with >149Kgates , and 484FBGA or 484UBGA
Cyclone V E 5CEFA7U19C8N 149Kgates 484UBGA $161.22 (digikey, In stock)
Cyclone V E 5CEFA7U19C8N 149Kgates 484UBGA $195.45 (buyaltera.com)
Cyclone V E 5CEFA7F23C8N 149Kgates 484FBGA $178.69 (buyaltera.com)
Cyclone V GX 5CGXFC7C7F23C8N 149Kgates 484FBGA $163.26 (digikey, In stock)
Cyclone V GX 5CGXFC7C7U19C8N 149Kgates 484UBGA $182.93 (digikey, In stock) Cyclone V E 5CEFA9F23C8N 301Kgates 484FBGA $188.07 (digikey, In stock)
Cyclone IV GX EP4CGX150CF23C7N 149Kgates 484FBGA $304.80 (digikey, In stock)
Cyclone IV GX EP4CGX150CF23C7N 149Kgates 484FBGA $369.50 (buyaltera.com)
Could be possible to make by ourselves the PCB layout of a Cyclone V 301,000 gates DEnano-clone? Any FPGA layout expert here?
However, more to the point is that a family using the FPGA 23x23mm @1mm pitch F484 usually have common pinouts within the same family. So a simple pcb with the FPGA, the flash to store the code and an SDRAM (or SRAM) and some I/O is all we really need on a pcb. I have been thinking about doing a generic style FPGA pcb for some time now, but I have never laid out an FPGA IC before and certainly not soldered one. I now have a benchtop oven so could probably solder them but they are expensive and I have no test gear to ensure correct soldering of the balls.
I also saw that the 5CGXFC7C7F23C8N was $197.92 (150K LE). Mouser is the same price, but some of their pricing is better than Digi.
That PDF is really worth a good chuckle! They are going to program the propeller chip (their cloned version) using Verilog - how???
They obviously do not understand anything about applications, only producing a chip virtually the same as the Prop.
Presume they didn't get any funding (if that was the ultimate exercise) because we've not heard of anything.
Anyway, back to the real topic....
IMHO the $179 Cyclone V seems like a good mid-range for testing provided it's easy to generate a new binary easily. The equivalent addon pcb we have for the DE0 & DE2 need to be designed outside Parallax (so we don't distract them).
I must say that the 1 cog version has certainly opened up the multi-task ideas and given some great feedback.
Oh dear!
I just quickly looked through the above mentioned PDF.
I should have payed attention to Bill's advice, I now have coffee sprayed all over my screen!
The "Conclusion" and "Future work" sections were quite amusing and yet disturbing at the same time.
The company name was a worry too...l. LOL
However, more to the point is that a family using the FPGA 23x23mm @1mm pitch F484 usually have common pinouts within the same family. So a simple pcb with the FPGA, the flash to store the code and an SDRAM (or SRAM) and some I/O is all we really need on a pcb. I have been thinking about doing a generic style FPGA pcb for some time now, but I have never laid out an FPGA IC before and certainly not soldered one. I now have a benchtop oven so could probably solder them but they are expensive and I have no test gear to ensure correct soldering of the balls.
I also saw that the 5CGXFC7C7F23C8N was $197.92 (150K LE). Mouser is the same price, but some of their pricing is better than Digi.
I've been very interested in the P2 emulation for quite some time. Unfortunately, my current project would require at least 2 cogs and the DE2-115 is out of my price range right now. The nano looks very promising but I can't justify getting one right now when I need more than a single cog. 2 cogs would work but more is better
A generic board would be great. I've never soldered BGA's but I think it would be possible. My big problem with investing in a development board is there is A LOT of stuff on these boards I would never use. If you do make a board, I would be very interested in one. Keep us posted!
Oh My God. I read through parts of that PDF... Thanks for linking it. I can't really do the whole thing.
The only point of interest to me was the market pie chart from 2008, and the class called "other" being larger than I thought it would be. Suggests many niche markets doing their own thing, good for us frankly. I'm off to find one from last year and do some digging. Kind of want to know what "other" means.
Yes, it's an impressive board. Mine is a little tiny bit less impressive due to the little RF connectors being chipped off. Won't ever use 'em, so no worries.
Student boards are about $200. I had a student, who I am mentoring in embedded / robotics things right now, buy one and it's on "loan" to me with the agreement they get it back, or it gets destroyed.
Terasic really isn't brutal about it. One does have to sign off on a kind of funny document that basically asserts, "We are selling this to you CHEAP, and we swear to God we know which board we sold you and if we EVER find it in a production setting...." and it kind of trails off from there as a legal warning threat of some kind. Can't blame 'em. I just thought it funny, not off putting as they intended. And some credible proof of being in school is needed. Not much. Student ID card and some relevant courses. I honestly think the "you will feel really bad about it" document will work more than it won't to prevent abuses. Good call on their part.
This is probably a one board per student, maybe, maybe two if there is a damn good reason like "I spilled on it", but still worth thinking about policy to keep it all in check. That price is probably Terasic's cost.
Anyway, when the announcement was made we did think about it, and it makes perfect sense for testing. I will probably explore FPGA development at some point on the thing too. The only real downside was their costs. Probably wouldn't make sense to have a run on these things, but a few for some potential early testers? Probably no big deal. And if they are at all interested in heading down the FPGA road, it's a sweet dev board with lots of great options. I shared my P1 stuff and some mentoring time, well not really as I would have done that anyway, in return for the purchase favor. Something to think about, if building cores on too many different boards is any kind of trouble / distraction.
Does anyone know what kind of score the people behind that 'document' got?
They don't know what latency really means, they seems to think that Spin was used during the design...
I'm not even certain if they know what Moore's law is all about...
However, more to the point is that a family using the FPGA 23x23mm @1mm pitch F484 usually have common pinouts within the same family. So a simple pcb with the FPGA, the flash to store the code and an SDRAM (or SRAM) and some I/O is all we really need on a pcb. I have been thinking about doing a generic style FPGA pcb for some time now, but I have never laid out an FPGA IC before and certainly not soldered one. I now have a benchtop oven so could probably solder them but they are expensive and I have no test gear to ensure correct soldering of the balls.
Good point.
For current FPGA 28nm I would prefer Altera to Xilinx just for that reason. I think they call it "vertical migration". You design your layout for 484 BGA (23x23) or (19x19), and you can choose the FPGA with the number of gates you really need.
Xilinx datasheet for Artix-7 said something about smaller FPGAs (-35 , -50, -75 ), but cannot find any other than model -100 and -200.
It looks to me that they still need to seel their stocked Spartan-6.
> I would prefer Altera to Xilinx just for that reason
Also if this is prop specific then Chip may have hand instantiated some Altera primitives in the Verilog code, and it would be work to change them. We certainly hand instantiate plenty of Xilinx specific things here at work. Mostly clock related, but potentially also I/Os and other macros. Plus having to learn the quirks of a different tool flow, etcetera.
My preference would be Xilinx because they appear cheaper for the same LEs. However, for this exercise, Altera is the WTG because that is what Chip is using.
It is a shame that the DE0 isn't built with the next size LEs because most worthwhile tests really need at least 2 cogs. That is why I think the $179 is an excellent fit.
Does anyone know if the emulation is using internal or external memory for the hub ram? (internal block memory inside the FPGA or SDRAM externally)
If it is internal I might just knock up a simple F484 pcb.
My preference would be Xilinx because they appear cheaper for the same LEs. However, for this exercise, Altera is the WTG because that is what Chip is using.
It is a shame that the DE0 isn't built with the next size LEs because most worthwhile tests really need at least 2 cogs. That is why I think the $179 is an excellent fit.
Does anyone know if the emulation is using internal or external memory for the hub ram? (internal block memory inside the FPGA or SDRAM externally)
If it is internal I might just knock up a simple F484 pcb.
I can see that, and it's impressive that ozprop managed to cram an entire game, with video generator, into one P2 cog with the added-at-last-minute threading features. But I wonder how much this sort of thing is going to be like programming an actual multi-cog P2? If Spin2 is anything like Spin1 then the interpreter will take most or all of a cog, leaving no room for threading-trick code. I would imagine we will still be normally booting to such an interpreted language, right? I'd rather be honing a style that will be typical of what is done with the actual chip.
Also, it occurs to me that while threading gives us in some ways the equivalent of a 32-cog P1, since multiple cog threads are deployed in a common cog memory space combining threaded code that does multiple functions is going to have to be done a bit differently than it is on P1 where something like, say, a single cog that soes both IIC and a serial channel (I've coded that) has to be custom assembled for each such potential combination. With threads it should be possible to write PASM2 modules that implement IIC and serial and somehow $include them in a cog PASM module that sensibly arranges them in memory and threads them. Is anybody working on that?
One of the main usability strengths of the Prop is one functionality = one object = one cog.
Not always true, but that's where it all starts. You want a functionality, serial, SD, whatever, grab the object from OBEX that does that and throw it into your project. As long as you have cogs free it will work.
Mixing up different functionalities into COGS each using a thread may never be that easy to do. Unless someone clever comes up with a means of combining PASM codes for different threads into a single COG blob and organize getting them started and reading their PAR parameters and so on.
Currently the SPIN 2 interpreter does not consume most of the COG. There is room for PASM snippets to be loaded in-line and executed. I'm unclear on how much room that is, but a lot of SPIN 2 will be loaded as snippets to be used by a smaller interpreter.
I believe SPIN will also task, but maybe I read that wrong.
The chip boots PASM. What happens from there is entirely up to the developer. SPIN 2 will be loaded. Something else could be loaded too.
@Heater, yes. Combining things won't be the same as simply launching a COG with them. However, it will be considerably easier to combine things that would not normally use up the COG than it is on P1.
I suspect the "multi-task COG BLOB" idea may well be something we can do with SPIN in a fairly standard way. Perhaps that done early will encourage PASM and LMM-PASM object authors to write with a few assumptions.
The deal is that I may write a serial driver, with it's own little PASM. You may write an I2C driver, with it's own little PASM.
Then random stranger Joe comes along and drops those into his own project with his own code. Boom it all works. Joe has used 3 cogs to do it.
But what if my serial PASM and your I2C PASM are small enough that they could fit to one COG and they don't need all the speed of a single COG?
How could we write our drivers in such a way that Joe could drop them into his project and Boom it works but Joe has only used 2 cogs now?
What kind of compiler/tool would we need to be able to do that?
This combining of PASM code has always been possible on the Prop 1, but it was not done much because it's complicated to do without the automatic thread scheduling and the Prop 1 has much less performance anyway.
Agreed that >1cog is necessary to do most testing. We cannot check out drivers or the like really without at least 2 cogs. But 2 cogs would suffice for a lot of testing.
Unfortunately, Chip is only human (although at times I really do wonder ) and cannot squeeze 2 cogs out of our cheap DE0's. Like many, I don't wish to spring $500-600 for a 5 cog version.
The DE0-Nano has a Cyclone IV EP4CE22F17C6N (22K LE's). The DE115 has 115K LE's and can do 5 cogs. So for a 2 cog P2 we require at least 44K LE's.
The Cyclone V seem better priced than the Cyclone IV (at least from Digi & Mouser). Here are some pricing..
FPGA484 LE COG FPGA256
5CEBA2F23C8N 25K 1 $37.76 ($34.81 for F17)
5CEBA4F23C8N 48K 2 $53.29 ($49.40 for F17)
5CEBA5F23C8N 76K 3 $88.04
5CEBA7F23C8N 149K 6 $159.36
5CEBA9F23C8N 301K 8 $209.76
So, I am looking at building a pcb for the FPGA484 Cyclone V family which would have...
Cyclone V 5CEBAnF23C8N
Flash config
SPI Flash (config P2) ?
SDRAM (for P2)
Hopefully 96 I/O
microSD socket
PropPlug header
Hopefully Circuitry for DACs etc (as per the DE0 expansion pcb from Parallax)
Cluso, I'm drooling over the thought of a 2 cog P2. My vote is for a 5CEBA4F23C8N *2cog*
Looks like they only come in multiples of 48 or 50 (mouser and digikey respectively.) So maybe a group-buy may be in order?
Comments
Wait a minute, do people actually drink water? Straight that is.
Wow!
I never imagined that the idea of +3 cogs would create so much debate.
The last thing I would ever want to do is waste Chip's time. It was an idea I just put out there.
Yes, we all want silicon but in reality we know that's a little way off. So in the meantime time we continue development.
Doesn't the description of this forum read as follows:
In the end this early development helps Parallax when they finally have silicon.
Lots of tools and examples,tutorials etc...
We all win
Cheers
Brian
Funny, I did the same exercise yesterday. Do you have a special discount with Digi? The 5CEFA9F23C8N is $228.00 for me http://www.digikey.com/product-search/en?lang=en&site=us&KeyWords=5CEFA9F23C8N&x=0&y=0
However, more to the point is that a family using the FPGA 23x23mm @1mm pitch F484 usually have common pinouts within the same family. So a simple pcb with the FPGA, the flash to store the code and an SDRAM (or SRAM) and some I/O is all we really need on a pcb. I have been thinking about doing a generic style FPGA pcb for some time now, but I have never laid out an FPGA IC before and certainly not soldered one. I now have a benchtop oven so could probably solder them but they are expensive and I have no test gear to ensure correct soldering of the balls.
I also saw that the 5CGXFC7C7F23C8N was $197.92 (150K LE). Mouser is the same price, but some of their pricing is better than Digi.
They obviously do not understand anything about applications, only producing a chip virtually the same as the Prop.
Presume they didn't get any funding (if that was the ultimate exercise) because we've not heard of anything.
Anyway, back to the real topic....
IMHO the $179 Cyclone V seems like a good mid-range for testing provided it's easy to generate a new binary easily. The equivalent addon pcb we have for the DE0 & DE2 need to be designed outside Parallax (so we don't distract them).
I must say that the 1 cog version has certainly opened up the multi-task ideas and given some great feedback.
I wish I could laugh at this ridiculous document. Instead, it makes me ill. These clods don't belong in a university.
I just quickly looked through the above mentioned PDF.
I should have payed attention to Bill's advice, I now have coffee sprayed all over my screen!
The "Conclusion" and "Future work" sections were quite amusing and yet disturbing at the same time.
The company name was a worry too...l. LOL
I've been very interested in the P2 emulation for quite some time. Unfortunately, my current project would require at least 2 cogs and the DE2-115 is out of my price range right now. The nano looks very promising but I can't justify getting one right now when I need more than a single cog. 2 cogs would work but more is better
A generic board would be great. I've never soldered BGA's but I think it would be possible. My big problem with investing in a development board is there is A LOT of stuff on these boards I would never use. If you do make a board, I would be very interested in one. Keep us posted!
The only point of interest to me was the market pie chart from 2008, and the class called "other" being larger than I thought it would be. Suggests many niche markets doing their own thing, good for us frankly. I'm off to find one from last year and do some digging. Kind of want to know what "other" means.
Yes, it's an impressive board. Mine is a little tiny bit less impressive due to the little RF connectors being chipped off. Won't ever use 'em, so no worries.
Student boards are about $200. I had a student, who I am mentoring in embedded / robotics things right now, buy one and it's on "loan" to me with the agreement they get it back, or it gets destroyed.
Terasic really isn't brutal about it. One does have to sign off on a kind of funny document that basically asserts, "We are selling this to you CHEAP, and we swear to God we know which board we sold you and if we EVER find it in a production setting...." and it kind of trails off from there as a legal warning threat of some kind. Can't blame 'em. I just thought it funny, not off putting as they intended. And some credible proof of being in school is needed. Not much. Student ID card and some relevant courses. I honestly think the "you will feel really bad about it" document will work more than it won't to prevent abuses. Good call on their part.
This is probably a one board per student, maybe, maybe two if there is a damn good reason like "I spilled on it", but still worth thinking about policy to keep it all in check. That price is probably Terasic's cost.
Anyway, when the announcement was made we did think about it, and it makes perfect sense for testing. I will probably explore FPGA development at some point on the thing too. The only real downside was their costs. Probably wouldn't make sense to have a run on these things, but a few for some potential early testers? Probably no big deal. And if they are at all interested in heading down the FPGA road, it's a sweet dev board with lots of great options. I shared my P1 stuff and some mentoring time, well not really as I would have done that anyway, in return for the purchase favor. Something to think about, if building cores on too many different boards is any kind of trouble / distraction.
They don't know what latency really means, they seems to think that Spin was used during the design...
I'm not even certain if they know what Moore's law is all about...
Sorry, my fault. I were using EUROS not $. (Prices today are still the same, in )
Good point.
For current FPGA 28nm I would prefer Altera to Xilinx just for that reason. I think they call it "vertical migration". You design your layout for 484 BGA (23x23) or (19x19), and you can choose the FPGA with the number of gates you really need.
Xilinx datasheet for Artix-7 said something about smaller FPGAs (-35 , -50, -75 ), but cannot find any other than model -100 and -200.
It looks to me that they still need to seel their stocked Spartan-6.
I think that the problem is that none of us will get the economies of scale (price reduction) that Terasic has.
I wonder (and some friend too) how they make money with DE0-nano. So not sure if they would make a low cost Cyclone V in near future.
Also if this is prop specific then Chip may have hand instantiated some Altera primitives in the Verilog code, and it would be work to change them. We certainly hand instantiate plenty of Xilinx specific things here at work. Mostly clock related, but potentially also I/Os and other macros. Plus having to learn the quirks of a different tool flow, etcetera.
It is a shame that the DE0 isn't built with the next size LEs because most worthwhile tests really need at least 2 cogs. That is why I think the $179 is an excellent fit.
Does anyone know if the emulation is using internal or external memory for the hub ram? (internal block memory inside the FPGA or SDRAM externally)
If it is internal I might just knock up a simple F484 pcb.
That $179 board is looking really interesting...
1) it should handle 3 cogs
2) it has enough memory for the full 128KB of rom/ram
3) it should be possible to map the "video dacs" to 24 bit RGB data for the HDMI out --> no adapter board needed!
I will probably buy one of those boards.
It has LPDDR2,I think arranged as 512MBx32, which does not fit the current emulations at all; however it also has 256KBx16 SRAM.
I'm in too! Even if the price is a little more than $179..
One cog is more fun than you might think.
C.W.
I can see that, and it's impressive that ozprop managed to cram an entire game, with video generator, into one P2 cog with the added-at-last-minute threading features. But I wonder how much this sort of thing is going to be like programming an actual multi-cog P2? If Spin2 is anything like Spin1 then the interpreter will take most or all of a cog, leaving no room for threading-trick code. I would imagine we will still be normally booting to such an interpreted language, right? I'd rather be honing a style that will be typical of what is done with the actual chip.
Also, it occurs to me that while threading gives us in some ways the equivalent of a 32-cog P1, since multiple cog threads are deployed in a common cog memory space combining threaded code that does multiple functions is going to have to be done a bit differently than it is on P1 where something like, say, a single cog that soes both IIC and a serial channel (I've coded that) has to be custom assembled for each such potential combination. With threads it should be possible to write PASM2 modules that implement IIC and serial and somehow $include them in a cog PASM module that sensibly arranges them in memory and threads them. Is anybody working on that?
You have a good question there.
One of the main usability strengths of the Prop is one functionality = one object = one cog.
Not always true, but that's where it all starts. You want a functionality, serial, SD, whatever, grab the object from OBEX that does that and throw it into your project. As long as you have cogs free it will work.
Mixing up different functionalities into COGS each using a thread may never be that easy to do. Unless someone clever comes up with a means of combining PASM codes for different threads into a single COG blob and organize getting them started and reading their PAR parameters and so on.
I believe SPIN will also task, but maybe I read that wrong.
The chip boots PASM. What happens from there is entirely up to the developer. SPIN 2 will be loaded. Something else could be loaded too.
@Heater, yes. Combining things won't be the same as simply launching a COG with them. However, it will be considerably easier to combine things that would not normally use up the COG than it is on P1.
I suspect the "multi-task COG BLOB" idea may well be something we can do with SPIN in a fairly standard way. Perhaps that done early will encourage PASM and LMM-PASM object authors to write with a few assumptions.
The deal is that I may write a serial driver, with it's own little PASM. You may write an I2C driver, with it's own little PASM.
Then random stranger Joe comes along and drops those into his own project with his own code. Boom it all works. Joe has used 3 cogs to do it.
But what if my serial PASM and your I2C PASM are small enough that they could fit to one COG and they don't need all the speed of a single COG?
How could we write our drivers in such a way that Joe could drop them into his project and Boom it works but Joe has only used 2 cogs now?
What kind of compiler/tool would we need to be able to do that?
This combining of PASM code has always been possible on the Prop 1, but it was not done much because it's complicated to do without the automatic thread scheduling and the Prop 1 has much less performance anyway.
Unfortunately, Chip is only human (although at times I really do wonder
The DE0-Nano has a Cyclone IV EP4CE22F17C6N (22K LE's). The DE115 has 115K LE's and can do 5 cogs. So for a 2 cog P2 we require at least 44K LE's.
The Cyclone V seem better priced than the Cyclone IV (at least from Digi & Mouser). Here are some pricing.. So, I am looking at building a pcb for the FPGA484 Cyclone V family which would have...
Looks like they only come in multiples of 48 or 50 (mouser and digikey respectively.) So maybe a group-buy may be in order?
Please keep us up to date on the developments!
Sounds fantastic! I would purchase one immediately. Kepp us informed!