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DE2i-150 An 8 cog emulator? — Parallax Forums

DE2i-150 An 8 cog emulator?

ozpropdevozpropdev Posts: 2,791
edited 2013-10-01 03:31 in Propeller 2
Hi Guys

As I eagerly await the arrival of my DE2-115 board (lots of pacing back and forth) I am reminded of a conversation I had
with "Tubular" on a discovery he made a couple of weeks ago. Altera - Terasic are releasing a 150k element board in November.
The DE2i-150 is the model number and It's going to be ~$50 cheaper as well.
Jumping from 115k to 150k might just squeeze in 8 cogs!
When I max out my 5 Cogs (It could happen),I might have somewhere to go?
Just putting it out there.
Thanks again to Tubular for finding this.

Cheers
Brian
«1

Comments

  • TubularTubular Posts: 4,622
    edited 2013-09-25 18:11
    Lol you're letting cats out of bags there, Brian. But since you have I've attached the summary table.

    Terasic_P2_Board_Comparison_16Sep13.png


    The latest news is the 3 new models should arrive "Nov/Dec" - they are currently sourcing materials for these boards. That may fit in well with when Chip is done with the current logic revision, and the $179-$299 multi cog boards might get more forumistas testing/developing

    I don't know how much faster the Cyclone V would be compared to the Cyclone IV. Not that Cyclone IV has been too slow for anything...

    Here are the website links to the 3 new boards. Beware the confusion as there will be 3 different DE2 models...
    $555 DE2i-150 http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=529
    $299 SoCKit http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816
    $179 C 5 GX http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830

    However, I'm very pleased to hear you're not waiting and about to receive your DE2-115. Fun times ahead
    Terasic_P2_Board_Comparison_16Sep13.png
    636 x 269 - 23K
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-09-25 19:51
    3 cogs for $179 would be a nice cheap version :)
  • SeairthSeairth Posts: 2,474
    edited 2013-09-25 20:06
    Cluso99 wrote: »
    3 cogs for $179 would be a nice cheap version :)

    Agreed! I was actually planning on buying the Nano, but if this would be an option, I just might hold off. What to do... what to do...
  • TubularTubular Posts: 4,622
    edited 2013-09-25 20:31
    Seairth wrote: »
    Agreed! I was actually planning on buying the Nano, but if this would be an option, I just might hold off. What to do... what to do...

    Go the DE0-Nano, Seairth. It's available, it's compact, it's cheap, and you can pack a heap into a cog now. By the time you truly outgrow it the other options might be available. Having the constraint there actually makes you explore the more advanced features. You can test out your ideas now.

    Our experience having both DE2 and DE0 available was to initially spread out into 3 cogs of the DE2, but then realize we could compact into the single cog of a DE0 using the excellent task switching. The hub ram is tight but having the SDRAM driver is ample backup for room to grow [providing you don't need very high res video].
  • jmgjmg Posts: 15,148
    edited 2013-09-25 20:39
    Tubular wrote: »
    I don't know how much faster the Cyclone V would be compared to the Cyclone IV. Not that Cyclone IV has been too slow for anything...

    They do look quite new :

    http://newsroom.altera.com/press-releases/nr-cyclone-v-soc-production-shipping.htm

    Just in full production, and 28nm - claims 900MHz Processor Clock speed on the Arm included.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-09-25 20:47
    3 cogs, full 128k of hub rom/ram, but 32 bit ddr2... or 4MB of 16 bit wide sram.

    Actually all three boards look interesting; the SOC has a dual core ARM, and the -150 has an Atom.
    Cluso99 wrote: »
    3 cogs for $179 would be a nice cheap version :)
  • rjo__rjo__ Posts: 2,114
    edited 2013-09-25 21:07
    I think there is a market here:)
    I'm dreaming of a Parallax intern doing all the work I don't want to do... and me buying my P2/FPGA direct from Parallax(USPS), with all the bells and whistles:)
  • jmgjmg Posts: 15,148
    edited 2013-09-25 21:12
    I also see first info on MachXO3 being released : (no details on package/prices yet)

    This claims up to 22k logic cells, as well as

    Built-in Interfaces – Hard MIPI, PCIe, and GbE IP cores simplify interfacing and bridging
    High Performance, Lowest Power – 150MHz fabric speed
    On-chip Regulators - Single supply solution that leverages on-chip regulators to simplify design
    Multi-time Programmable (MTP) Technology
    High-Speed SERDES – Support for 3.125Gbps transceivers
    includes DSP and memory resources

    The largest part here, might support 1 Prop 2 COG ? - and I wonder how much of a Prop 1 ?
  • Heater.Heater. Posts: 21,230
    edited 2013-09-25 23:26
    Yep, I could be tempted by the Cyclone V GX Starter Kit.

    The others start to get way over any kind of budget I can explain away to "her in doors".

    Especially as the bigger boards come with far more sophistication, ARM/ATOM integration etc, than I will ever have time to explore. Besides we don't need that expensive junk to exercise the Propeller 2 design, just a bigger FPGA.
  • nutsonnutson Posts: 242
    edited 2013-09-26 06:18
    I have a DE2-115, and have ordered both the Terasic SocKit (C5 with 110K LE's) and the C5 Starter (C5 with 77K LE's). Some remarks pro and contra wanting another FPGA variant of the P2.

    - We want silicon, everything that keeps Chip from realizing that goal asap hurts.

    - I have not seen any example using more than 3 COG's on the DE2-115 yet, we are not out of possibilities there

    - SoCKit delivery expected October, C5 Starter November?

    - DE2-150 with a separate Intel Atom processor has a PCIe interface to the FPGA, complicated. The SOC kit has the ARM processor on chip with the FPGA with a very fast parallel interface.

    + The Cyclone V family has inherited many features from the Arria family (8 input LUT's, fractional PLL's, 3 GBit transceivers, dual port 32x20 memories made from ALM's). C5 is not going to be faster than C4 (take Stratix for that) but I would not be surprised if it a 3-4 COG P2 could be done in the 77K LE's. This could tempt more developers into purchasing such a $179 kit and have a positive influence on the development of software and drivers for P2.
  • ozpropdevozpropdev Posts: 2,791
    edited 2013-09-26 06:39
    Hi Nutson

    Some very valid points there, but may I add a few comments here.
    Chip will probably have to generate new binaries for the DE0 & DE2 anyway to verify the tweaks he has made to the core.
    nutson wrote: »
    I have not seen any example using more than 3 COG's on the DE2-115 yet, we are not out of possibilities there

    I don't know about anyone else but the code I am working on at the moment requires 5 cogs.
    I have other work that will require more....
  • David BetzDavid Betz Posts: 14,511
    edited 2013-09-26 06:48
    nutson wrote: »
    - I have not seen any example using more than 3 COG's on the DE2-115 yet, we are not out of possibilities there.
    Well, I have a program that uses all 5 COGs on a DE2-115 board but it's just a dumb demo to prove that I can get C code running on all of them. It just blinks LEDs so it doesn't count as a program that actually does useful things with all 5 COGs.
  • RamonRamon Posts: 484
    edited 2013-09-26 07:38
    ozpropdev wrote: »
    Hi Guys

    As I eagerly await the arrival of my DE2-115 board (lots of pacing back and forth) I am reminded of a conversation I had
    with "Tubular" on a discovery he made a couple of weeks ago. Altera - Terasic are releasing a 150k element board in November.
    The DE2i-150 is the model number and It's going to be ~$50 cheaper as well.
    Jumping from 115k to 150k might just squeeze in 8 cogs!
    When I max out my 5 Cogs (It could happen),I might have somewhere to go?
    Just putting it out there.
    Thanks again to Tubular for finding this.

    Cheers
    Brian

    Hi,

    DE2i-150 is priced at $555.

    We could beg Terasic for making a 'DE nano' with Cyclone V E 301Kgates:

    Current prices at Digikey and Altera for : stocked & cheapest Cyclone IV or V with >149Kgates , and 484FBGA or 484UBGA

    Cyclone V E 5CEFA7U19C8N 149Kgates 484UBGA $161.22 (digikey, In stock)
    Cyclone V E 5CEFA7U19C8N 149Kgates 484UBGA $195.45 (buyaltera.com)
    Cyclone V E 5CEFA7F23C8N 149Kgates 484FBGA $178.69 (buyaltera.com)
    Cyclone V GX 5CGXFC7C7F23C8N 149Kgates 484FBGA $163.26 (digikey, In stock)
    Cyclone V GX 5CGXFC7C7U19C8N 149Kgates 484UBGA $182.93 (digikey, In stock)
    Cyclone V E 5CEFA9F23C8N 301Kgates 484FBGA $188.07 (digikey, In stock)
    Cyclone IV GX EP4CGX150CF23C7N 149Kgates 484FBGA $304.80 (digikey, In stock)
    Cyclone IV GX EP4CGX150CF23C7N 149Kgates 484FBGA $369.50 (buyaltera.com)


    Could be possible to make by ourselves the PCB layout of a Cyclone V 301,000 gates DEnano-clone? Any FPGA layout expert here?
  • photomankcphotomankc Posts: 943
    edited 2013-09-26 07:39
    nutson wrote: »
    I have a DE2-115, and have ordered both the Terasic SocKit (C5 with 110K LE's) and the C5 Starter (C5 with 77K LE's). Some remarks pro and contra wanting another FPGA variant of the P2.


    I have to agree to some extent. I see no reason to plan a whole major project on silicon that is not realized yet so why is it necessary to get an 8 cog variant out? Not rhetorical, is there a real need that people see there?

    The 1 and 5 cog versions seem well sufficient to prove out critical parts of the puzzle and even to develop a set of core drivers for certain functions up-front but it would seem to me to be effort wasted to develop the 8 core version just to let people develop bigger test apps. Those apps may be impressive but are they really doing something that can't be demonstrated with 5 cores?
  • Dave HeinDave Hein Posts: 6,347
    edited 2013-09-26 07:54
    An 8-cog version could test out corner cases that aren't tested in a 5-cog version. This would allow testing the result of a coginit when all cogs are running, and whether there is any effect on cog 0's hub accesses when cog 7 is running. Sure, this stuff should work, but it's probably worth testing it if possible.
  • nutsonnutson Posts: 242
    edited 2013-09-26 07:55
    @ozpropdev

    Thanks for your great Invaders game, a good example of the P2 possibilities.

    My comments boil down to:
    - lets be carefull what we ask for (Chip triggers easily sometimes...)
    - if any I would vote for the Terasic Cyclone V starter board because of the lower cost..

    Chip is verifying his design on a Stratix III board, so that will be done anyway. The work involved in porting a Verilog design to another board is changing and verifying all connections and pin definitions to the board resources (expansion connectors, RAM etc) and maybe PLLdefinitions. But I am worried that doing this for DE0-nano and DE2-115 and ..... can become too taxing

    Are you in Verilog design? I made a (limited) P1 Verilog model years ago for the DE1 board and ported this to the DE2-70 and DE2-115 later.

    To my great surprise I found a Propeller 1 Verilog design (source code!!) on the Internet recently (google on multi-core microprocessor interface, the link to sjsu.edu points to an PDF). I wonder if Parallax cooperated on this
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-09-26 08:49
    I took a quick peek at the pdf...

    Chip will be surprised to learn that the Propeller 1 was designed using Spin and assembly language!

    These gentlemen want to design a clone, using Verilog and C, and they want to operate as a fabless chip house like ARM, licensing their Verilog.

    I also found p.32 very interesting, note the $12,000.00 for licensing the Linux (operating system), salaries etc.

    The PDF looks like a prospectus for trying to get investors.

    Edit: They do have verilog code in the PDF for a cog .... I wonder if it works?
  • pedwardpedward Posts: 1,642
    edited 2013-09-26 09:39
    These guys (3 of them) were going for a Master's degree and this was their final project. Their proposal paper is riddled with inaccuracies and errors (they misspelled Parallax). In a normal context I wouldn't be so harsh on folks, but I'm holding them to a high level of accountability because there are 3 of them and they are in a Master's degree program.

    Right away I'd have given them demerits for inaccuracy in their proposal, because they clearly don't understand the big picture, they only understand the small scope. A good engineer must understand the big picture and be capable of focusing on the small as well. This is precisely what makes Chip so excellent at what he does. Chip has an exceptional ability to expand his thought process beyond what he's working on at the moment and see the big picture.

    For the record, the Propeller 1 was designed in AHDL and the final routing was all done by hand with Chip and Beau.

    The SPIN and PASM languages run *on* the Propeller chip!

    I see they also had "Patent costs" in their proposed budget. I'd love to hear the explanation of what patents they planned to pursue on technology they cloned from an existing product that had been around for > 3 years at the time.
  • nutsonnutson Posts: 242
    edited 2013-09-26 09:55
    Bill, the code might work, but if you look at the module definition around line 20 of the source code:

    module cog (I_out,clock,reset);
    output [31:0] I_out;
    input clock,reset;

    This code describes a single processor with an internal memory of 512x32 (that does not get filled), a limited number of opcodes and only one output. So it is nowhere near a real Propeller.
  • Dave HeinDave Hein Posts: 6,347
    edited 2013-09-26 10:47
    The third author of the document, Sanket Shah, posted to the forum a few times asking questions. You can find his posts by searching for "Sanket".
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-09-26 11:03
    I did catch the lack of reference to a hub... so basically, its a single cog, with limited functionality.

    I think several forum members have done more in the past :)
    nutson wrote: »
    Bill, the code might work, but if you look at the module definition around line 20 of the source code:

    module cog (I_out,clock,reset);
    output [31:0] I_out;
    input clock,reset;

    This code describes a single processor with an internal memory of 512x32 (that does not get filled), a limited number of opcodes and only one output. So it is nowhere near a real Propeller.
  • David BetzDavid Betz Posts: 14,511
    edited 2013-09-26 11:35
    nutson wrote: »
    Bill, the code might work, but if you look at the module definition around line 20 of the source code:

    module cog (I_out,clock,reset);
    output [31:0] I_out;
    input clock,reset;

    This code describes a single processor with an internal memory of 512x32 (that does not get filled), a limited number of opcodes and only one output. So it is nowhere near a real Propeller.
    Maybe Chip will open-source the AHDL for P1 and we can all help convert it to Verilog! He mentioned at the Open Hardware Summit that he might open-source the P2 RTL at some point after the chip was in production.
  • jmgjmg Posts: 15,148
    edited 2013-09-26 12:03
    Dave Hein wrote: »
    An 8-cog version could test out corner cases that aren't tested in a 5-cog version. This would allow testing the result of a coginit when all cogs are running, and whether there is any effect on cog 0's hub accesses when cog 7 is running. Sure, this stuff should work, but it's probably worth testing it if possible.

    Good point, but that test coverage could be checked with 3 stubs that acted like 'COGs wanting HUB'.
  • nutsonnutson Posts: 242
    edited 2013-09-26 12:51
    David, it would be very exiting to have a single COG P1 model that we could interface to resources on any FPGA board or our own designed peripherals in the FPGA. Imagine a SPIN decoder...an FFT butterfly peripheral ....

    Language conversion is not needed. Quartus can compile projects with modules written in defferent styles. One step further: it is posible to distribute IP without disclosing source code. Many design examples that Terasic provides with its DE-boards contain encrypted IP modules, that you can use in a design (license provided) without knowing the content. The NIOS processor is always delivered as encrypted IP. But I am not sure what is needed to create encrypted IP. Maybe only Altera can do this.
  • Heater.Heater. Posts: 21,230
    edited 2013-09-26 13:41
    Bill,
    I took a quick peek at the pdf..
    Do you have the link for that, I need a good laugh.
  • nutsonnutson Posts: 242
    edited 2013-09-26 13:46
    Google on "multi-core microprocessor interface", the link to sjsu.edu points to the PDF
  • Heater.Heater. Posts: 21,230
    edited 2013-09-26 14:11
    nutson,

    Thanks, first thing I read is:

    "This design is mainly focused on increasing the latency of the processor which is to be used for embedded applications."

    This could keep me in giggles all night!
  • KeithEKeithE Posts: 957
    edited 2013-09-26 14:19
    There are not any non-blocking assigns in the verilog. It's not clear to me that this code would synthesize correctly.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-09-26 14:39
    http://generalengineering.sjsu.edu/docs/pdf/mse_prj_rpts/fall2009/Multi-Core%20Microprocessor%20Interface.pdf

    Just don't drink any water around your computer while reading it...
    Heater. wrote: »
    Bill,

    Do you have the link for that, I need a good laugh.
  • nutsonnutson Posts: 242
    edited 2013-09-26 14:40
    My guess is the Verilog code has only been run in a simulator with a testbench of some ten instructions as in appendix D

    But there are universities that stimulate their students to real good and interesting projects.

    http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/

    http://people.ece.cornell.edu/land/courses/ece4760/FinalProjects/
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