DEMO: Another Sigma Delta ADC
Beau Schwabe
Posts: 6,566
I was exploring this over the weekend and thought it was worth posting. The output seems extremely stable down to +/-1 LSB .... If anybody is willing I would like to see a definitive comparison to some of the other ADC techniques that are out there.
"Theory:
Note: A key feature with this sigma-delta ADC is that the drive pin is set to an input shortly after the sample
period. A Typical configuration usually has the drive pin always set as an output and driven either HIGH
or LOW and the external analog input is connected to a node I have labeled as "A". That method creates more
of a voltage overshoot as the ADC tries to search introducing unnecessary noise. By placing the analog
input on the drive pin, the analog signal is blocked from the feedback pin during the sample period. When
the drive pin becomes an input the analog signal is then allowed to charge or discharge the capacitor. In
this way you minimize antenna effects caused by long distances from the analog source that would normally
interfere during a sample period.
"
"Theory:
Note: A key feature with this sigma-delta ADC is that the drive pin is set to an input shortly after the sample
period. A Typical configuration usually has the drive pin always set as an output and driven either HIGH
or LOW and the external analog input is connected to a node I have labeled as "A". That method creates more
of a voltage overshoot as the ADC tries to search introducing unnecessary noise. By placing the analog
input on the drive pin, the analog signal is blocked from the feedback pin during the sample period. When
the drive pin becomes an input the analog signal is then allowed to charge or discharge the capacitor. In
this way you minimize antenna effects caused by long distances from the analog source that would normally
interfere during a sample period.
"
Comments
Is this an approach that would work better with a DIP chip on a breadboard?
I remember that the regular sigma-delta has noise issues with long wires and works best with SMT parts really close to Prop pins.
It sounds like you're saying this is more tolerant of longer wires...
I started to analyze your scheme to add up and balance the current into the summing junction.
Your drive pin is going full high or full low for one clock cycle each time around the loop, and the current drawn through the 470Ω from the external source voltage during that time is (Vi / 470) or ((Vi - Vdd)/ 470). That is quite a load fluctuation to apply to the source. From the standpoint of the integrator, it too sees a larger fluctuation, currents of +/- 1.65 / 10000 during the single clock cycle, and +/-(Vi - 1.65)/10470 during the rest of the cycle. To a first approximation. Hmmm.
Hey! your one of the guys I was hoping to take a look at this. The 470 is mainly there to protect the drive pin in the case of a wiper on the pot being at one extreme or the other. Other than that it's fairly low current (I think) ... As far as the standard method, "...creates more of a voltage overshoot", I feel as though that method spends more time than necessary either charging or discharging the cap... just a case of over saturation if you will.
Rayman,
This is just something I stumbled on serendipitously, and liked the stability of the readings. ... and things are pretty well spread out (see video link below)
pedward,
There is a small program I found called "dopdf-7" from a company called "Softland" that creates a virtual printer that you just print to. The result is a PDF
The only caveat I notice is that there is a small but slightly noticeable electrical 'detent' at exactly the mid value. You don't feel the detent per say, but rather you can observe it. In the case of a potentiometer with a center return, this is ideal (in my opinion). By adjusting the currently fixed 10k in the schematic the detent can be adjusted. i.e narrowed or widened
Video Reference:
http://www.youtube.com/watch?v=on9Vs0Sv0GE&feature=youtu.be
I'm having some problems correlating the claims with the drawing.
In a classic SDM, a true integrator is used, and that does not care what amplitude the triangle+sawtooth on the D-FF sampler is. (provided it does not clip)
Indeed, if lowest power is the goal, spending more time away from the Pin-threshold, helps lower Icc, so you might see 25-33% Vcc triangle components.
It also removes the pin threshold from the equation.
In a Prop, you can remove the true integrator, using just a RC, with some compromises :
* The pin threshold now matters - it becomes the reference zero, if you will.
* The True long-term Analog Integration the integrator gave, is removed, but the counter is used to 'claw some back'
Your circuit now has three currents to balance. The Vu injection, plus the Pin Feedback (1/6 weighted) and the Pot Wiper (5/6 weighted)
The pin threshold seems to have become a larger factor, which leads to ...
'Flat spots' should not exist in a true integration SDM, but they can be an artifact of the trade-off of using a RC.
I think the 3rd current path makes this worse, as a small charge that does not quite get over the threshold on the first sample, can discharge via the 3rd current path, and the issue repeats, as there is no cycle-cycle accumulation.
Your video demo does look quite stable at ~10 bits, especially given the loose layout on the white plugboard. How does that hold up, say if you shoot for 12 bits?
At clkfreq=80MHz, your loop is 6 pasm instructions, so the loop is executing at 3.33MHz. That is a lot more relaxed for loose wiring than the counter-based ADC, and in and of itself might give more stable readings. 5 instructions with the drive pin as input, 1 instruction cycle (50ns) with it as an output opposite the feedback.
For analysis, I'd start with a stiff voltage source at the input, rather than a potentiometer. The source resistance of the potentiometer complicates the calculations as it is 5000Ω at the wiper center and zero Ω at the ends. That in series with the 10470Ω of fixed resistors during the sampling period. Makes it nonlinear.
When I some time ago was experimenting a lot with the delta sigma adc of the prop I came to the following "model of thinking":
There is a certain voltage region for the input, where it is not at all defined, whether this is high or low. In this region the decision Hi or Low is completely by chance or by influences inside the propeller. This leads to noise of results.
In this thinking model your setup and result seems to say, that it is better to have no load to be driven during the decision. So no other cog should disturb things meanwhile!
Perhaps the decision is good to be done by logic that is some µm farer away from the output.
Christof
BTW, has anybody tried a more clever filtering method than the usual moving average, which has a rather poor frequency response? In true sigma delta ADCs more sophisticated filters are used (sinc² or something).
The biggest improvement I've found in the sigma delta ADC is to shut off the PLL and run directly off the crystal. Using the sigma delta circuit on the quickstart, I was able to get 13-14 bits of resolution with a 10Hz sample rate running at 5MHz. I also got 13-14bits resolution at 80MHz clock 10Hz ADC, but the 5MHz results show me that with an 80MHz crystal oscillator a sigma delta ADC could hit 16-bits of resolution with a 10Hz sample rate.
Lawson
I'm not quite following. You say 'improvement', but the absolute figures you then give, are the same ?
Once the ADC hits the noise floor, the expected gain from higher MHz will not eventuate, but you figures suggest it does not get worse either.
(and the MHz likely benefits other operations, even if it has no gain on ADC)
In a Prop, the Pin input buffer has almost no Power supply rejection, and so the internal noise of Vcc and Gnd will also be a factor.
An ideal simple ADC should hit 15.6 bits in 10Hz, at ~500KHz, and that is ~ 33uV of equivalent threshold
13.3 bits, is 165uV of of equivalent threshold floor.
At 80MHz it is hard to find a reasonable priced Opamp good enough to integrate , but at 500KHz it should be possible
Shutting down the PLL is an improvement because PLL jitter/noise adds about 2-bits worth of noise. It just happens that running 16x faster adds enough more samples that averaging makes up the difference. ( I.e. the uncertainty of an average gets better proportional to sqrt(n) where "n" is the number of samples) I also did testing at PLL2x, performance was worse than running without the PLL at 5MHz.
Lawson
Interesting, I wonder if that is time-domain, or voltage domain (aka more Vcc.Gnd noise) ?
Be interesting to see what a moderately good OpAmp can do, as an external integrator moves the threshold from a Digital-Pin-In-Linear-Mode, to an OpAmp input. Something better than 20v/us could be worth trying ?