After running the demo drivers on my Viewsonic monitor, I had an interesting idea...
What if the VSync/HSync/DotCLK timings the monitor reported were accurate?
The timings were VESA standard, but maybe the Insignia only liked 60Hz VSync
I used the Viewsonic to figure out FREQA values that gave me VESA standard 60Hz VSync with appropriate VESA standard HSync and dot clocks for all three VGA demos (1280x1024, 800x600, 640x480) and now all of those modes work on my Insignia!
Here are the working FREQA values:
640x480 use $0D80_0000
800x600 use $1510_0000
1280x1024 use $3A00_0000
Now those values are mathematically higher than we would expect, so I think that we have some PLL inaccuracy on the DE0-Nano - which may vary from nano to nano.
The PLL on my nano seems to be 3.57% too fast, your mileage may vary.
My boards arrived today. For what it's worth, I got a NANO board along with the DE2, and I don't have a NANO FPGA. Keep me in mind should somebody need the NANO board. I can send it somewhere.
I've been on a work project and am reading back through to find the correct or current FPGA file. If one of you sees this and has a quick link to it handy, please post it. Thanks.
For testing, I have an HDTV Plasma display, CRT VGA and CRT NTSC component capable standard definition TV.
My boards arrived today. For what it's worth, I got a NANO board along with the DE2, and I don't have a NANO FPGA. Keep me in mind should somebody need the NANO board. I can send it somewhere.
I've been on a work project and am reading back through to find the correct or current FPGA file. If one of you sees this and has a quick link to it handy, please post it. Thanks.
For testing, I have an HDTV Plasma display, CRT VGA and CRT NTSC component capable standard definition TV.
My boards arrived today. For what it's worth, I got a NANO board along with the DE2, and I don't have a NANO FPGA. Keep me in mind should somebody need the NANO board. I can send it somewhere.
I've been on a work project and am reading back through to find the correct or current FPGA file. If one of you sees this and has a quick link to it handy, please post it. Thanks.
For testing, I have an HDTV Plasma display, CRT VGA and CRT NTSC component capable standard definition TV.
I got my boards today. This is probably a dumb question but what is the correct orientation for the PropPlug on each board? I don't see anything on the board saying which pin is which. I guess it probably won't hurt to plug it in backwards but I'd like to minimize my chances of blowing anything up.
I got my boards today. This is probably a dumb question but what is the correct orientation for the PropPlug on each board? I don't see anything on the board saying which pin is which. I guess it probably won't hurt to plug it in backwards but I'd like to minimize my chances of blowing anything up.
Okay, thanks! I thought Bill meant that "Vss" was actually printed on his board. For future reference, is there any danger if the PropPlug is plugged in backwards?
Obviously not, because I just went through the same exercise. Had to pull the flash chip due to some program being on it. Between that and not being sure which way the plug goes, I thought I had broken something.
Bill's 1024 VGA displaying nicely on my CRT VGA.
I have the flash pulled and it's all working well now. Face the Prop Plug label toward the prototype area on the adapter board. (for those reading through getting setup)
Obviously not, because I just went through the same exercise. Had to pull the flash chip due to some program being on it. Between that and not being sure which way the plug goes, I thought I had broken something.
Bill's 1024 VGA displaying nicely on my CRT VGA.
I have the flash pulled and it's all working well now. Face the Prop Plug label toward the prototype area on the adapter board. (for those reading through getting setup)
I don't understand this issue with needing to pull the SPI flash chip. Doesn't the P2 work like the P1 where it first tries to boot from the serial connection and only goes to the SPI flash when the serial load times out?
I don't understand this issue with needing to pull the SPI flash chip. Doesn't the P2 work like the P1 where it first tries to boot from the serial connection and only goes to the SPI flash when the serial load times out?
Yes, I took the lazy way, mostly because I've not yet worked through accessing the chip. The monitor is last in the chain. Suppose a program could be written to check a pin too. Flip a switch, get the monitor. Maybe just insert that code as a default. That's probably what I'll do, maybe fire off a monitor on another COG. That way, programming happens on one port, there is always a monitor with the running program on the other.
Just ran through the VGA examples. All of them displayed in a stable way. The 640 and 800 pixel ones do not fill the screen. Looking at them now to understand whether or not they are supposed to fill the screen.
Bill's 1024 pixel example displayed perfectly as well.
Sorry about the ambiguity on the PropPlug orientation. I didn't think about this when reviewing the layout. What I did, later, was check for the square pad on the underside of the board which indicates VSS (GND) and then I knew which way to plug it in. It won't hurt if it goes in backwards, as there's no power supply connection on those 4 pins - only VSS and 3 signals.
Thanks, but it Chip's demo, timing modified by me for 1024x768. Only other thing I did was move all the relevant timing parameters together, and rename them to more closely match the VESA standard parameter names (in an abbreviated form) so its easier to adapt to other resolutions with different timings.
I got my DE2-115 reprogrammed and hooked up to the new add-on board but I have a question. Are all of the LEDs still connected to the same Propeller pins? The pin doc seems to imply they are but when I run my multi-cog demo program that flashes LED0-5 LED 4 doesn't flash. Each LED is flashed by a different COG and they all used to flash before I reprogrammed the FPGA. Is LED4 disconnected in this new configuration?
I got my DE2-115 reprogrammed and hooked up to the new add-on board but I have a question. Are all of the LEDs still connected to the same Propeller pins? The pin doc seems to imply they are but when I run my multi-cog demo program that flashes LED0-5 LED 4 doesn't flash. Each LED is flashed by a different COG and they all used to flash before I reprogrammed the FPGA. Is LED4 disconnected in this new configuration?
P32..P43 all output to LED's. I think last time it started at P48.
P32..P43 all output to LED's. I think last time it started at P48.
I'm using P32-P37 in the multi-cog demo. I know LED4 works because it comes on dimly when the board powers up. Is anything else connected to that pin besides the LED?
I'm using P32-P37 in the multi-cog demo. I know LED4 works because it comes on dimly when the board powers up. Is anything else connected to that pin besides the LED?
I wrote a simple one COG program that blinks the 6 LEDs and that seems to be working fine so there isn't a problem with the LED itself or the connection of the LED to the Propeller pin.
My multi-cog demo uses a funky token passing scheme to pass control from one COG to the next. When a COG gets the token it changes its blink rate. That isn't happening even with the COGs that are sucessfully blinking LEDs. Is there any chance that COG 5 isn't working? That would explain why LED 4 isn't blinking and also why the other LEDs don't change blink rates.
Edit: I just modified my multi-cog demo to use only 5 COGs and it is working fine including flashing LED4. I think I'm having trouble with COG 5.
@ Sapieha re: If it is this board kit send by Ken --- Some of components are missing and some incorrect
It's the batch that Chip arranged to send out. I just got it from Parallax on Friday. It a completed board, not a kit.
So far I have only tried the following:
1. Upload the new file to the FPGA(all ok)
2. Plug the board into the FPGA and power it up(all ok)
3. Run Andy's Cordic demo program to see that it's still basically working (all ok)
4. Download the Prop2 GCC package (to learn how to run it)
My next steps are to:
Try the simple VGA demo that Chip made.
Try some of the P2 GCC examples.
After running the demo drivers on my Viewsonic monitor, I had an interesting idea...
What if the VSync/HSync/DotCLK timings the monitor reported were accurate?
The timings were VESA standard, but maybe the Insignia only liked 60Hz VSync
I used the Viewsonic to figure out FREQA values that gave me VESA standard 60Hz VSync with appropriate VESA standard HSync and dot clocks for all three VGA demos (1280x1024, 800x600, 640x480) and now all of those modes work on my Insignia!
Here are the working FREQA values:
640x480 use $0D80_0000
800x600 use $1510_0000
1280x1024 use $3A00_0000
Now those values are mathematically higher than we would expect, so I think that we have some PLL inaccuracy on the DE0-Nano - which may vary from nano to nano.
The PLL on my nano seems to be 3.57% too fast, your mileage may vary.
Bill,
Do you have the jumper in place as mentioned in the Pinouts.txt file?
For DE0-Nano, jumper pin 3 to pin 5 on the 2 x 13 header to
establish the video PLL loop:
(view from bottom of DE0-Nano)
+-----------------------------------+
| O o o o o o o o o o o o o o O |
| o o o o o o o o o o o=o o |
| |
Comments
Nico Hattink
What if the VSync/HSync/DotCLK timings the monitor reported were accurate?
The timings were VESA standard, but maybe the Insignia only liked 60Hz VSync
I used the Viewsonic to figure out FREQA values that gave me VESA standard 60Hz VSync with appropriate VESA standard HSync and dot clocks for all three VGA demos (1280x1024, 800x600, 640x480) and now all of those modes work on my Insignia!
Here are the working FREQA values:
640x480 use $0D80_0000
800x600 use $1510_0000
1280x1024 use $3A00_0000
Now those values are mathematically higher than we would expect, so I think that we have some PLL inaccuracy on the DE0-Nano - which may vary from nano to nano.
The PLL on my nano seems to be 3.57% too fast, your mileage may vary.
I've been on a work project and am reading back through to find the correct or current FPGA file. If one of you sees this and has a quick link to it handy, please post it. Thanks.
For testing, I have an HDTV Plasma display, CRT VGA and CRT NTSC component capable standard definition TV.
Appreciated.
My old COMPAQ FS7600 is about to see some signals...
I have not checked the DE2 board yet.
VSS are on same side that this text
Bill's 1024 VGA displaying nicely on my CRT VGA.
I have the flash pulled and it's all working well now. Face the Prop Plug label toward the prototype area on the adapter board. (for those reading through getting setup)
You don't need pull it out --- If You first write any program that erase it and start it at first activity
Bill's 1024 pixel example displayed perfectly as well.
@ Sapieha
Very unique design. :smile:
If it is this board kit send by Ken --- Some of components are missing and some incorrect
http://forums.parallax.com/showthread.php/146153-Prop-II-DE0-NANO-Emulator-PCB?p=1168337&viewfull=1#post1168337
.
P32..P43 all output to LED's. I think last time it started at P48.
My multi-cog demo uses a funky token passing scheme to pass control from one COG to the next. When a COG gets the token it changes its blink rate. That isn't happening even with the COGs that are sucessfully blinking LEDs. Is there any chance that COG 5 isn't working? That would explain why LED 4 isn't blinking and also why the other LEDs don't change blink rates.
Edit: I just modified my multi-cog demo to use only 5 COGs and it is working fine including flashing LED4. I think I'm having trouble with COG 5.
re: If it is this board kit send by Ken --- Some of components are missing and some incorrect
It's the batch that Chip arranged to send out. I just got it from Parallax on Friday. It a completed board, not a kit.
So far I have only tried the following:
1. Upload the new file to the FPGA(all ok)
2. Plug the board into the FPGA and power it up(all ok)
3. Run Andy's Cordic demo program to see that it's still basically working (all ok)
4. Download the Prop2 GCC package (to learn how to run it)
My next steps are to:
Try the simple VGA demo that Chip made.
Try some of the P2 GCC examples.
So far so good.
Bill,
Do you have the jumper in place as mentioned in the Pinouts.txt file?
For DE0-Nano, jumper pin 3 to pin 5 on the 2 x 13 header to establish the video PLL loop: (view from bottom of DE0-Nano) +-----------------------------------+ | O o o o o o o o o o o o o o O | | o o o o o o o o o o o=o o | | |