Funny you should mention that - I think this may be the second time I've heard of the autorouting function . My traces were done by hand (over....and over....again). Still haven't found the autorouting function on KiCad ^o^
Funny you should mention that - I think this may be the second time I've heard of the autorouting function . My traces were done by hand (over....and over....again). Still haven't found the autorouting function on KiCad ^o^
Autorouting features are mostly found in more heavier tools like Mentor Graphics and Altium Designer. I'm using AD10 &, believe me, you're not missing anything for not using autorouting.
Funny you should mention that - I think this may be the second time I've heard of the autorouting function . My traces were done by hand (over....and over....again). Still haven't found the autorouting function on KiCad ^o^
To move the reset trace to the top of the board, I'd move R1 a bit to the left, then move the trace from pin 2 of R1 to the right of R1, and run it between pins 2 and 3 of P1. Then you can run the trace from pin 1 of R1 between pins 1 and 2 of P1, and then between pins 1 and 44 of U3.
Click the Roadsign on the toolbar in PCB New. It opens up FreeRouter (via Java Web Start). You just export the design to FreeRouter, route, then import it back it. As a side note, I like to do much of my hand trace re-arranging in FreeRouter, since it also has a very nice push and shove tool that KiCad does not.
Don't forget to move the labels (R1, C4, U3, etc.) from under the components so that you can see them when the board is populated.
100nF caps provide for high frequency bypass. 1uF provides a bulk capacitance and is usually shared between a number of pins. What I have seen on the parallax pcbs is a single 1uF cap for all prop pins. With your circuit you will get awau with almost anything but that isnot the correct way. Even a 10nF helps higher frequencies.
I prefer to use a larger bulk cap like 4.7uF or 10uF for the prop plus up to 4 x 100nF. The bulk cap can be shared with the output of the vreg mcp1700 provided it is close to theprop power connections/plane.
(evemgnd should read 3v3/gnd on next line g unable to fix with my xoom)
Addie, just remember, we all have different requirements and are overkill for your simple design. I use proper evemgnd planes and caps because I require my props to run safely when overclocking to 104MHz.
100nF caps provide for high frequency bypass. 1uF provides a bulk capacitance and is usually shared between a number of pins. What I have seen on the parallax pcbs is a single 1uF cap for all prop pins.
So I've just sent the board off *yikes!* and now that the deed is done, I'm already looking at rev 2 haha. But I was wondering about what you said here about the 1uF being shared between a number of pins. So I'm doublechecking that this means that all of my VSS pins can be connected to one side of a 1uF and all of my VDD pins can be connected to the other.
I ask only because I assumed that each VSS/VDD pairing needed its own decoupling cap as close to it as possible? Or is the distance in my pcb negligible?
I think it is very exciting sending off a board for production. Tempting as it is to send off revision 2 before revision 1 arrives, I seem to find that there is always that one little improvement that you find as you solder up revision 1 that saves having to skip to revision 3
For an "ideal" design you usually want a 100nF (0.1uF) capacitor for each of the Vdd/Vss pairs coming off the chip. This capacitor provides a small amount of power for the portion of the chip connected to those power pins when that portion suddenly switches state and demands some amount of peak power. There's a small amount of resistance from one side of the chip to another and having a capacitor for each pair of power leads avoids the voltage drop across the chip. You also want a 1uF to 10uF capacitor for the whole board (particularly with a small board and only a few ICs). This fills in the power demands for the board itself given that there may be a few inches of wire to maybe a couple of feet of wire from there to the actual power supply. If you've got a wall-wart a few feet away or a USB cable providing power, you might want the larger value with a 100nF capacitor in parallel.
If you've got the Vdd/Vss pairs connected under the chip with very short, thick traces, you can probably do fine with a single 100nF in parallel with a 1uF. In Cluso99's case, he's overclocking and the power demands go up as the square of the speed, so he needs really good bypassing.
For an "ideal" design you usually want a 100nF (0.1uF) capacitor for each of the Vdd/Vss pairs coming off the chip. This capacitor provides a small amount of power for the portion of the chip connected to those power pins when that portion suddenly switches state and demands some amount of peak power. There's a small amount of resistance from one side of the chip to another and having a capacitor for each pair of power leads avoids the voltage drop across the chip. You also want a 1uF to 10uF capacitor for the whole board (particularly with a small board and only a few ICs). This fills in the power demands for the board itself given that there may be a few inches of wire to maybe a couple of feet of wire from there to the actual power supply. If you've got a wall-wart a few feet away or a USB cable providing power, you might want the larger value with a 100nF capacitor in parallel.
If you've got the Vdd/Vss pairs connected under the chip with very short, thick traces, you can probably do fine with a single 100nF in parallel with a 1uF. In Cluso99's case, he's overclocking and the power demands go up as the square of the speed, so he needs really good bypassing.
So at this point I'm doing the bill of materials and have "in the cart" 4 0.1uf caps for the decoupling (even though they're labeled 1uf on the board), and the other 1uf caps, well they're still 1uf caps. So....I'm going to assume this is a better idea than using 1uF caps for the decoupling ones, but you're saying that for such a small board, it'd also be smart to have a general 1-10uf cap (for rev 2!)
Yes. Remember that these are RC and LC circuits and, the larger the capacitor, the lower the frequency it can respond to. These are very very fast ICs and 1uF capacitors are too big to respond well to demands for power. 100nF (0.1uF) is better. The board level capacitor can be 1uF or 10uF because it doesn't have to respond to the high speed transients that occur in nanosecond or sub-nanosecond timeframes. It can respond over hundreds of nanoseconds or over microseconds where the power is poking along over the couple of feet from the wall-wart. Look at this video clip about signal propagation in wire by Rear Admiral Grace Hopper. Years ago, I heard her talk about this and she would pass out "nanoseconds". It's lost now, but I had one of those for years.
Gotcha - that makes sense. Sorry for repeating pretty much what you said for extra clarification . Thanks for the suggestion, I'll include it on rev 2!
Yes. Remember that these are RC and LC circuits and, the larger the capacitor, the lower the frequency it can respond to. These are very very fast ICs and 1uF capacitors are too big to respond well to demands for power. 100nF (0.1uF) is better.
Well its not quite that simple - the inductance of the leads from the chip die to the chip package is probably the limiting factor, followed by the pcb trace inductance,
only then does the decoupling cap get a look-in and ceramic chip capacitors are inherently low ESL, the fast edges will "see" enough of the dielectric
before the pulse has even crossed the width of the capacitor (the speed of electricity inside the ceramic dilelectric is maybe 100 times slower than in the wires
leading to it due to its ferroelectric nature)
The capacitor has to start to reflect back the fast edge inverted (as its an effective short-circuit) back through the pcb trace and bonding leads back on to the chip die
before the fast edge has finished (you want to cancel out most of the magnitude of the voltage excursion). Switching transients are steps not sinusoids and standard
analog circuit theory breaks down here and is misleading.
There's a great book (prob out of print) "Digital Hardware Design" by Catt, Walton and Davidson (ISBN 0333259815) that goes through the real theory of digital
waveforms and decoupling which is basically the same as the telegraph theory developed by Heaviside more than a century ago, but scaled down in size and
up in frequency.
Comments
Autorouting features are mostly found in more heavier tools like Mentor Graphics and Altium Designer. I'm using AD10 &, believe me, you're not missing anything for not using autorouting.
Your board seems to look cool, by the way
To move the reset trace to the top of the board, I'd move R1 a bit to the left, then move the trace from pin 2 of R1 to the right of R1, and run it between pins 2 and 3 of P1. Then you can run the trace from pin 1 of R1 between pins 1 and 2 of P1, and then between pins 1 and 44 of U3.
Click the Roadsign on the toolbar in PCB New. It opens up FreeRouter (via Java Web Start). You just export the design to FreeRouter, route, then import it back it. As a side note, I like to do much of my hand trace re-arranging in FreeRouter, since it also has a very nice push and shove tool that KiCad does not.
Don't forget to move the labels (R1, C4, U3, etc.) from under the components so that you can see them when the board is populated.
I prefer to use a larger bulk cap like 4.7uF or 10uF for the prop plus up to 4 x 100nF. The bulk cap can be shared with the output of the vreg mcp1700 provided it is close to theprop power connections/plane.
(evemgnd should read 3v3/gnd on next line g unable to fix with my xoom)
Addie, just remember, we all have different requirements and are overkill for your simple design. I use proper evemgnd planes and caps because I require my props to run safely when overclocking to 104MHz.
So I've just sent the board off *yikes!* and now that the deed is done, I'm already looking at rev 2 haha. But I was wondering about what you said here about the 1uF being shared between a number of pins. So I'm doublechecking that this means that all of my VSS pins can be connected to one side of a 1uF and all of my VDD pins can be connected to the other.
I ask only because I assumed that each VSS/VDD pairing needed its own decoupling cap as close to it as possible? Or is the distance in my pcb negligible?
I think it is very exciting sending off a board for production. Tempting as it is to send off revision 2 before revision 1 arrives, I seem to find that there is always that one little improvement that you find as you solder up revision 1 that saves having to skip to revision 3
It's a Purple Heart
For an "ideal" design you usually want a 100nF (0.1uF) capacitor for each of the Vdd/Vss pairs coming off the chip. This capacitor provides a small amount of power for the portion of the chip connected to those power pins when that portion suddenly switches state and demands some amount of peak power. There's a small amount of resistance from one side of the chip to another and having a capacitor for each pair of power leads avoids the voltage drop across the chip. You also want a 1uF to 10uF capacitor for the whole board (particularly with a small board and only a few ICs). This fills in the power demands for the board itself given that there may be a few inches of wire to maybe a couple of feet of wire from there to the actual power supply. If you've got a wall-wart a few feet away or a USB cable providing power, you might want the larger value with a 100nF capacitor in parallel.
If you've got the Vdd/Vss pairs connected under the chip with very short, thick traces, you can probably do fine with a single 100nF in parallel with a 1uF. In Cluso99's case, he's overclocking and the power demands go up as the square of the speed, so he needs really good bypassing.
So at this point I'm doing the bill of materials and have "in the cart" 4 0.1uf caps for the decoupling (even though they're labeled 1uf on the board), and the other 1uf caps, well they're still 1uf caps. So....I'm going to assume this is a better idea than using 1uF caps for the decoupling ones, but you're saying that for such a small board, it'd also be smart to have a general 1-10uf cap (for rev 2!)
Well its not quite that simple - the inductance of the leads from the chip die to the chip package is probably the limiting factor, followed by the pcb trace inductance,
only then does the decoupling cap get a look-in and ceramic chip capacitors are inherently low ESL, the fast edges will "see" enough of the dielectric
before the pulse has even crossed the width of the capacitor (the speed of electricity inside the ceramic dilelectric is maybe 100 times slower than in the wires
leading to it due to its ferroelectric nature)
The capacitor has to start to reflect back the fast edge inverted (as its an effective short-circuit) back through the pcb trace and bonding leads back on to the chip die
before the fast edge has finished (you want to cancel out most of the magnitude of the voltage excursion). Switching transients are steps not sinusoids and standard
analog circuit theory breaks down here and is misleading.
There's a great book (prob out of print) "Digital Hardware Design" by Catt, Walton and Davidson (ISBN 0333259815) that goes through the real theory of digital
waveforms and decoupling which is basically the same as the telegraph theory developed by Heaviside more than a century ago, but scaled down in size and
up in frequency.
Never thought of it that way.... that's a really neat way to put some perspective on it.