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Propeller II programing questions to Chip

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  • AribaAriba Posts: 2,690
    edited 2013-04-07 09:02
    There are other such Pseudo-Instructions. I've found that TESTB reg,#bit is the same as ISOB reg,#bit NR

    Andy
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-09 15:00
    Hi Chip.


    How I can in PNut write that table.
    tab1_  org  $         '';direct commands 
       Byte "list"                                                        ' Any place in assembly code
       Word list         ''shr 8 + 128,list and 255                                 ' Any place in assembly code
       Byte "run"
       Word run             ''shr 8 + 128,run and 255    '<----------------- Original in 8080 assembly BYTE,BYTE
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-10 00:58
    Hi Chip.

    Forget it.

    I found my problem --- If I use WORD's it adds 0 to fill LONG's --- That disturbed my scan routine.
    Now That are fix
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-10 01:29
    Ps to previous post.

    That function for me.
    tab1_  org  $         '';direct commands 
       Byte "list"
       byte $80+list>>8,list         ''shr 8 + 128,list and 255
       Byte "run"
       byte $80+run>>8,run             ''shr 8 + 128,run and 255
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-19 03:11
    Hi Chip.

    Are $1F6,$1F7 (INDA, INDB] direct addressable else can this position can be used for other usage ?

    And INDA, INDB can only be addressed by SETINDA,SETINDB
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-21 14:55
    Hi Chip.

    What are difference between this 2 RET instructions

    And Can You give syntax examples on one that are different from Propeller 1
    ''000111 ZC0 1 CCCC 000000000 000000000    |   RET        |           | ''Return from subroutine            4 *
''111010 001 1 1111 000000000 000000000    |   RET        |           | ''Like JMP, but assembler handles details
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-04-21 18:24
    Sapieha wrote: »
    Hi Chip.

    What are difference between this 2 RET instructions

    And Can You give syntax examples on one that are different from Propeller 1
    ''000111 ZC0 1 CCCC 000000000 000000000    |   RET        |           | ''Return from subroutine            4 *
''111010 001 1 1111 000000000 000000000    |   RET        |           | ''Like JMP, but assembler handles details
    My list shows opcode 111010 as CFGPINS & INCMOD.
    There is opcode 111010 which is JMPRETD, a delayed JMPRET.
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-21 18:39
    Hi Cluso.

    Thanks.

    Cluso99 wrote: »
    My list shows opcode 111010 as CFGPINS & INCMOD.
    There is opcode 111010 which is JMPRETD, a delayed JMPRET.
  • SapiehaSapieha Posts: 2,964
    edited 2013-04-21 18:47
    Hi Cluso.

    I have.
    I see I need test them by PNut.
    010111 ZCR 0 CCCC DDDDDDDDD SSSSSSSSS        JMPRETD D,S     ''jump to S, store return in D      1

000111 ZCR 0 CCCC DDDDDDDDD SSSSSSSSS        JMPRET  D,S     ''jump to S, store return in D      4 *
000111 ZCR 1 CCCC DDDDDDDDD nnnnnnnnn        JMPRET  D,#n     ''jump to 0..511, store return in D 4 *

111010 000 I CCCC DDDDDDDDD SSSSSSSSS   |   CFGPINS     |   D/#n    | Setup pins masked by register &#8220;D (0-511)&#8221; to register

111010 ZCR I CCCC DDDDDDDDD SSSSSSSSS   |   INCMOD      |   D,S#n   | Increment D between 0 and S. Wraps around to 0 when above S
  • SapiehaSapieha Posts: 2,964
    edited 2013-08-02 00:28
    Hi Chip.

    Have You any updates on Instructions, counters block diagrams and other things we can have play with ?
  • cgraceycgracey Posts: 14,151
    edited 2013-08-02 10:09
    Sapieha wrote: »
    Hi Chip.

    Have You any updates on Instructions, counters block diagrams and other things we can have play with ?

    Not yet.

    I'm getting close to having the new Spin interpreter running. This is taking all my work time, for now.
  • eldonb46eldonb46 Posts: 70
    edited 2013-08-02 13:14
    Chip, by chance, are you including new SPIN constructs to access the four tasks per COG of the Prop II?

    see: http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1122712#post1122712

    Thanks,
    Eldonb46
  • SapiehaSapieha Posts: 2,964
    edited 2013-08-02 13:42
    Hi Chip.

    Thanks for reply.

    Good look with SPIN

    cgracey wrote: »
    Not yet.

    I'm getting close to having the new Spin interpreter running. This is taking all my work time, for now.
  • Bill HenningBill Henning Posts: 6,445
    edited 2013-08-02 14:33
    Chip,

    I think all of us are looking forward to Spin for Prop2 :-) so it is really nice to hear it is close!
    cgracey wrote: »
    Not yet.

    I'm getting close to having the new Spin interpreter running. This is taking all my work time, for now.
  • cgraceycgracey Posts: 14,151
    edited 2013-08-02 16:38
    eldonb46 wrote: »
    Chip, by chance, are you including new SPIN constructs to access the four tasks per COG of the Prop II?

    see: http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1122712#post1122712

    Thanks,
    Eldonb46

    Yes. The interpreter uses the top half (actually, less) of cog RAM, as well as the top part of the stack RAM, PTRB, INDB, and SPB. This leaves free for PASM code (which could be multitasking): the first half+ of cog RAM, the first part of stack RAM, PTRA, INDA, and SPA.
  • SapiehaSapieha Posts: 2,964
    edited 2013-08-02 16:55
    Hi Chip.

    Look's as nice solution

    cgracey wrote: »
    Yes. The interpreter uses the top half (actually, less) of cog RAM, as well as the top part of the stack RAM, PTRB, INDB, and SPB. This leaves free for PASM code (which could be multitasking): the first half+ of cog RAM, the first part of stack RAM, PTRA, INDA, and SPA.
  • Heater.Heater. Posts: 21,230
    edited 2013-08-03 06:32
    Chip,Now that is interesting.
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