The topic line on this page seems to have changed back and forth between PLC and CPLD but assuming you want a CPLD, they do seem to be mainly PLCC chips, but you could always use an adapter eg http://www.futurlec.com/PLCC_Adapters.shtml
I'm kind of interested in this too - I tend to build things with 74xx chips and get PCBs made but that can take 2-3 weeks to get the boards made. Programming a CPLD would be a lot faster.
I wonder about a generic propeller and CPLD pair, where you devote some pins to comms (maybe an 8 bit bus plus a /rd and /wr pin) and then you get a propeller with lots of I/O pins, but you then can define all those pins with the software you write for the CPLD.
Any CPLD experts know how many macrocells you need to, say, emulate an 8080?
Ya im thinking my best bet is going to be a 44pin PLCC CPLD package with socket and either and adapter or a custom break out pcb. The sockets at futurelec are fairly cheap most others are around 20. From reading all of JMGs info I just think that the ATMEL stuff is going to be way over my head. Im really thinking of just getting the xilinx breakout board on dangerous proto types it has the chip and other goodies for a little more than a plcc to socket. This thread has got me thinking that every time something really stands in my way I build a tool to overcome it and at this point I need to do something about PCBs becuase etching is just not for me. Ive been doing a little research on how to cheaply put these stepper I have to good use.
Newer ones are TQFP, or QFN, but Altera, Xilinx and Atmel do all supply PLCC44 CPLDs.
If using an adaptor, you would need to customise local Vdd decoupling caps, for that vendor pin out.
Smallest CPLDs are QFN32, if size is your thing.
In QFN32 from Xilinx XC2C32 you get 32 macrocells.
in QFN32 from Lattice MachXO2, you get 256 LCells, and soon in the iCE40 family, 384 LCells.
I'm kind of interested in this too - I tend to build things with 74xx chips and get PCBs made but that can take 2-3 weeks to get the boards made. Programming a CPLD would be a lot faster.
I wonder about a generic propeller and CPLD pair, where you devote some pins to comms (maybe an 8 bit bus plus a /rd and /wr pin) and then you get a propeller with lots of I/O pins, but you then can define all those pins with the software you write for the CPLD.
The FPGA/Verilog tools do tend to be Multi-Gigabyte, and somewhat slow, but good for complex designs.
The simpler Atmel WinCUPL is much smaller at ~20MB, and can compile a source file like any assembler, in sub 1 second times.
Good for IO/State engine tasks, but I would not suggest WinCUPL for SoftCPU design, for example.
Ya im thinking my best bet is going to be a 44pin PLCC CPLD package with socket and either and adapter or a custom break out pcb. The sockets at futurelec are fairly cheap most others are around 20. From reading all of JMGs info I just think that the ATMEL stuff is going to be way over my head.
Ballpark, how many 74xx chips can that emulate (I'm thinking 40-60c cost for the 74xx chip plus the cost of the PCB real estate) - how do things compare?
Ballpark, how many 74xx chips can that emulate (I'm thinking 40-60c cost for the 74xx chip plus the cost of the PCB real estate) - how do things compare?
Each MACROCELL is a register, so 3 x C573's is 24 Macrocells ( but could need anything from 32+ to 48+ io lines )
Each decode line in a '138 is simply one pin (=1 macrocell) and one single line of code.
You are more likely to be pin-bound on a 44 pin part, so might have to bump to TQFP100, where you can have a thirsty 9572 at $6.90,
or a 128 macrocell, lower Icc ATF1508RE, or ATF1508ASVL, at ~ $4
I'm playing around with the idea of an "8080" style bus for the propeller. one /rd line, one /wr line, A0-A7 and D0-D7. So 18 pins, and that is encoded/decoded into 11 or 12 propeller pins. So if you have a common bus like that, then address the first CPLD as 00000000 and the second as device 00000001 etc you can add many I/O pins. Or use one with more pins like you say.
Another thought - type in 'plcc socket' into google images and looking at the PCB layout, that is a standard 0.1" spacing eg http://www.plccsocket.com/ So you don't need an adapter board - just the sockets. Should be as easy to solder as DIP
Yes, but that board has JTAG excluded, it just gives a MiniDIN connector.
You still need to get PC-JTAG solved. Parallel ports can do it cheap, if you still have some ?
I'm playing around with the idea of an "8080" style bus for the propeller. one /rd line, one /wr line, A0-A7 and D0-D7. So 18 pins, and that is encoded/decoded into 11 or 12 propeller pins. So if you have a common bus like that, then address the first CPLD as 00000000 and the second as device 00000001 etc you can add many I/O pins. Or use one with more pins like you say.
18 user side pins, plus 12 Prop-side pins gives 30, so you have 32io plus 4 ip on a typical CPLD.
You can encode an address into a JED file quite easily (for a security project we did some years back, we created a shipload of batch-build JED files, each uniquely serialised ), or, if you have pins spare, you can use a few as Address pins, for a mix like i2c.
The boffins here http://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/ seem to be using a pic to program the CPLD. It looks like the PIC is simply functioning as a serial to jtag translator. If so, the propeller ought to be able to provide the same function. Maybe then you don't even need a programmer?
If so, the propeller ought to be able to provide the same function. Maybe then you don't even need a programmer?
Yes, if you can swallow the file parser for the SVF file I pasted in #27, into a Prop, then you just need to get that file to the Prop. Copy/drag/drop or whatever.
Some handshake would be needed, as there are some delays in the SVF script, but I don't think large buffers are needed.
Apart from the delay operands, data/clock info simply passes on. Basically you have Operand Count and Pin.
A key question then, is how much Prop resource, would a SVF parser really need ?
I've attached a full SVF file, generated for a 32 Macrocell ATF1502BE, and I'd expect these to macrocell-scale.
They are using standard terminal programs. So - serial into a propeller for an ascii byte, and then wiggle some pins. I was hoping to see a code example.
The full resources of the prop would be available because you would program the prop to be a jtag programmer, then once the cpld is programmed, send another program to the eeprom. The prop can wiggle pins much faster than the serial data can come in, so I presume no need for large buffers.
The hardware would presumably be a few jumpers that temporarily join prop pins to the programming pins on the cpld.
and that v4 is not finished yet, so their link code must be a subset of SVF, and they have a intermediate exe to compress/shuffle SVF into what they can use.
Reading the first link more, maybe they have most of (x)SVF, and just do the init/device ID etc via their own
JTAG codes. It does say JTAG (3) -> XSVF player ?
Programming cables for Altera and Xilinx are dirt cheap, there is no need to buy a BusPirate. Just buy the cable and connect it to your parallel port and you're ready to go. If you don't have a parallel port, get a USB variant.
If you're really, really strapped for money like some here are, just build the parallel port adapter programmer, there are plans for both Xilinx and Altera out there who can't afford the $12 cables. it should only cost a few dollars. I just don't get trying to use a Prop for this, when it is already dirt simple. All the Prop does is add a another step and layer of complexity to a simple operation.
Comments
I'm not up on all the part numbers but I think these are altera CPLDs that would fit in these sockets http://www.futurlec.com/ICAltera.shtml
Interesting thread here http://www.eevblog.com/forum/beginners/altera-epm3032-cpld-guide-tour-please/ with a newbie asking the sort of newbie questions I'd be asking (like which gigabyte sized file is the right one to download!).
I'm kind of interested in this too - I tend to build things with 74xx chips and get PCBs made but that can take 2-3 weeks to get the boards made. Programming a CPLD would be a lot faster.
I wonder about a generic propeller and CPLD pair, where you devote some pins to comms (maybe an 8 bit bus plus a /rd and /wr pin) and then you get a propeller with lots of I/O pins, but you then can define all those pins with the software you write for the CPLD.
Any CPLD experts know how many macrocells you need to, say, emulate an 8080?
You need an FPGA for that:
http://opencores.org/project,cpu8080
Newer ones are TQFP, or QFN, but Altera, Xilinx and Atmel do all supply PLCC44 CPLDs.
If using an adaptor, you would need to customise local Vdd decoupling caps, for that vendor pin out.
Smallest CPLDs are QFN32, if size is your thing.
In QFN32 from Xilinx XC2C32 you get 32 macrocells.
in QFN32 from Lattice MachXO2, you get 256 LCells, and soon in the iCE40 family, 384 LCells.
The FPGA/Verilog tools do tend to be Multi-Gigabyte, and somewhat slow, but good for complex designs.
The simpler Atmel WinCUPL is much smaller at ~20MB, and can compile a source file like any assembler, in sub 1 second times.
Good for IO/State engine tasks, but I would not suggest WinCUPL for SoftCPU design, for example.
There is a useful quick read page here, complete with reports and complete source code example.
http://members.shaw.ca/Botgoodies2/CPLD/CPLD.htm
and for Flexible/Generic JTAG this looks interesting
http://dangerousprototypes.com/docs/Bus_Pirate_JTAG_XSVF_player
So that should PGM any pld device that the tools can generate .SVF for.
Seems there are 2 flavours
http://sandboxelectronics.com/store/index.php?main_page=product_info&products_id=185
and the slightly newer, larger-micro variant, for a little more $.
http://www.seeedstudio.com/depot/bus-pirate-v4-for-developers-p-740.html?cPath=174
but perhaps this v4 is still a little bit too new ?
http://dangerousprototypes.com/2012/08/09/bus-pirate-v4-back-in-stock-3/
http://dangerousprototypes.com/docs/Bus_Pirate_v4_vs_v3_comparison
says
*What doesn't work on Bus Pirate v4 right now:
XSVF player JTAG programmer .. hmmm...
unclear if SVF on v4 will work using external firmware ?
Thanks Leon - very useful info.
Ok, how about emulating three 373 latches and a 138 - would that fit in one of those small CPLDs?
Addit: found some xilinx ones at futurlec http://www.futurlec.com/Xilinx.shtml
eg 72 macrocells for $3.90.
Ballpark, how many 74xx chips can that emulate (I'm thinking 40-60c cost for the 74xx chip plus the cost of the PCB real estate) - how do things compare?
Each MACROCELL is a register, so 3 x C573's is 24 Macrocells ( but could need anything from 32+ to 48+ io lines )
Each decode line in a '138 is simply one pin (=1 macrocell) and one single line of code.
You are more likely to be pin-bound on a 44 pin part, so might have to bump to TQFP100, where you can have a thirsty 9572 at $6.90,
or a 128 macrocell, lower Icc ATF1508RE, or ATF1508ASVL, at ~ $4
PLCC sockets means you can remove the chip, put it in a programmer (right?) and then put it back on the board. eg http://www.ebay.com.au/itm/CPLD-Development-Board-Programmer-Kit-Jtag-/181003465800?pt=LH_DefaultDomain_0&hash=item2a24a5b448
Or put a 5x2 header on the board for JTAG?
I'm playing around with the idea of an "8080" style bus for the propeller. one /rd line, one /wr line, A0-A7 and D0-D7. So 18 pins, and that is encoded/decoded into 11 or 12 propeller pins. So if you have a common bus like that, then address the first CPLD as 00000000 and the second as device 00000001 etc you can add many I/O pins. Or use one with more pins like you say.
Another thought - type in 'plcc socket' into google images and looking at the PCB layout, that is a standard 0.1" spacing eg http://www.plccsocket.com/ So you don't need an adapter board - just the sockets. Should be as easy to solder as DIP
Intriguing possibilities.
Yes, but that board has JTAG excluded, it just gives a MiniDIN connector.
You still need to get PC-JTAG solved. Parallel ports can do it cheap, if you still have some ?
18 user side pins, plus 12 Prop-side pins gives 30, so you have 32io plus 4 ip on a typical CPLD.
You can encode an address into a JED file quite easily (for a security project we did some years back, we created a shipload of batch-build JED files, each uniquely serialised ), or, if you have pins spare, you can use a few as Address pins, for a mix like i2c.
Real parallel port plus some HC125s? Or the more modern way USB to JTAG for $12 http://www.ebay.com.au/itm/AVR-USB-JTAG-Emulator-Debugger-Programmer-Atmel-ATMega16-64-128-169-3-23-/280844195676?pt=AU_B_I_Electrical_Test_Equipment&hash=item41639e575c
I found another vendor, who seems to have two variants of the same PCB ?
http://stores.ebay.com.au/Marcmart-AU/_i.html?_nkw=JTAG&submit=Search&_sid=1061893871
and still more JTAG choices here...
http://dx.com/s/JTAG
the issue with all this is that while the price is low, the SW is vague, and does not mention which one(s) support SVF driver ?
The boffins here http://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/ seem to be using a pic to program the CPLD. It looks like the PIC is simply functioning as a serial to jtag translator. If so, the propeller ought to be able to provide the same function. Maybe then you don't even need a programmer?
Yes, that links to the same Bus Pirate using a PIC24, which was sumarised in the link I gave above
http://dangerousprototypes.com/docs/Bus_Pirate_v4_vs_v3_comparison
Yes, if you can swallow the file parser for the SVF file I pasted in #27, into a Prop, then you just need to get that file to the Prop. Copy/drag/drop or whatever.
Some handshake would be needed, as there are some delays in the SVF script, but I don't think large buffers are needed.
Apart from the delay operands, data/clock info simply passes on. Basically you have Operand Count and Pin.
A key question then, is how much Prop resource, would a SVF parser really need ?
I've attached a full SVF file, generated for a 32 Macrocell ATF1502BE, and I'd expect these to macrocell-scale.
They are using standard terminal programs. So - serial into a propeller for an ascii byte, and then wiggle some pins. I was hoping to see a code example.
The full resources of the prop would be available because you would program the prop to be a jtag programmer, then once the cpld is programmed, send another program to the eeprom. The prop can wiggle pins much faster than the serial data can come in, so I presume no need for large buffers.
The hardware would presumably be a few jumpers that temporarily join prop pins to the programming pins on the cpld.
There was a link on this link, but it seems broken
http://hackaday.com/2008/12/01/bus-pirate-firmware-update-v0c-jtag-and-more/
the table on this link
http://dangerousprototypes.com/docs/Bus_Pirate_v4_vs_v3_comparison
says XSVF player (JTAG)* integrated(v4) external firmware (v3)
and that v4 is not finished yet, so their link code must be a subset of SVF, and they have a intermediate exe to compress/shuffle SVF into what they can use.
Reading the first link more, maybe they have most of (x)SVF, and just do the init/device ID etc via their own
JTAG codes. It does say JTAG (3) -> XSVF player ?
They do link to a Xilinx appnote
http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf
and page 3 has a link to Source code ( you need to sign in to Xilinx )
SVF does not have that many opcodes, and you could easily fit 4 char keyword strings into longs, and simply compare on each new byte.
Along the lines of
{TRST}
{ABSE}
{ENDI}
{ENDD}
{HDR }
{HIR }
{TDR }
{TIR }
{RUNT}
{TCK;}
{SIR }
{TDI }
{TDO }
{SDR }
{STAT}
{IDLE}
{RESE}
{MASK}
{SEC;}
{E-6 }
so far that's ~20 parser tokens.
If you're really, really strapped for money like some here are, just build the parallel port adapter programmer, there are plans for both Xilinx and Altera out there who can't afford the $12 cables. it should only cost a few dollars. I just don't get trying to use a Prop for this, when it is already dirt simple. All the Prop does is add a another step and layer of complexity to a simple operation.
http://www.programmableplanet.com/author.asp?doc_id=252935&f_src=ProgrammablePlanet_report
Still just an idea, but claims to combine a ZYNQ7010 (DualARM9 + FPGA) and a Epiphany-III Chip, (65nm) an array of 16 Floating point processors....