CPLD in a DIP package?
rwgast_logicdesign
Posts: 1,464
For the life of me I cant find the thread any more but someone was talking about a PLC from Atmel in a dip package, does anyone know the name of these chips and whats needed to program them. I tried doing a little research on this before when I knew the chip name and couldnt figure out what kind of programmer of software I would need. I was thinking a DIP plc on a breadboard would be a good way to learn or even maybe bundle all the 74x chips in a project into these little dip plc's
Comments
You mean PLD (programmable logic device), not PLC (programmable logic controller). Here's a PLC:
-Phil
I.e. they don't require a clock to operate, like a micro does.
I ask because if they operate statically they wouldn't require
radio emission testing for commercial products like micro do.
Duane J
They do not have to be clocked, but usually are.
If they are clocked, the speed can often be very low, and they cannot suffer a SW crash like a Micro can.
Something like the classic Gate/Door controller can be designed with a 10ms state clock.
I think you mean PLD, not PLC, and Atmel is correct
{ you can edit your title }
http://www.atmel.com/products/other/spld-cpld/default.aspx
They have the following
The parts with Vpp.ParallelProgrammer, need a Universal Programmer, but the JTAG ISP ones can use just a JTAG link.
(this needs 4 pins committed as JTAG)
Software needed is WinCUPL, for Boolean Equation entry
http://www.atmel.com/tools/WINCUPL.aspx
Code is simple enough, somewhere between ASM and C,
/* Operators are # is OR, $ is XOR, & is AND */ /* example, Opcode is a 4 Macrocell Group (field) and MyAdr is a sticky Boolean (using a T FF) */ FIELD OpCode = [OpCode3..OpCode0]; OpcWa = MyAdr & (OpCode : 'b'0000); /* and you can also code state engines like */ SEQUENCED Qf { /* D FF state engine */ PRESENT 'b'00 IF (Qi:'b'01) OUT CLK_U; /* this first, then a clock is generated to re-sync Qf == Qi */ IF !CLK_Un NEXT 'b'01; /* CLK_Un is a node that collects CLK_U, and pulses once for every UP edge */ IF (Qi:'b'10) OUT CLK_D; IF !CLK_Dn NEXT 'b'10; /* CLK_Dn is a node that collects CLK_D, and pulses once for every DN edge */ IF (Qi:'b'11) OUT Illegal; /* optional catch invalid , can be power up */ $IFDEF ReSyncOnError IF (Qi:'b'11) NEXT 'b'11; $ENDIF default NEXT 'b'00; PRESENT 'b'01 IF (Qi:'b'11) OUT CLK_U; IF !CLK_Un NEXT 'b'11; IF (Qi:'b'00) OUT CLK_D; IF !CLK_Dn NEXT 'b'00; IF (Qi:'b'10) OUT Illegal; /* optional catch invalid , can be power up */ $IFDEF ReSyncOnError IF (Qi:'b'10) NEXT 'b'10; $ENDIF default NEXT 'b'01; /* more here */ } FIELD Sel = [Sel1..Sel0]; Edge = (Qa $ Qaa) # (Qb $ Qbb); /* A change in either Qa or Qb, gives one pulse */ Phase.ck = CLK; /* implied in ATF16V8, needed in Multiple CLK parts */ Phase0.d = !Phase0; /* Divide ALE by two, gives wider pulses, and ensures Tsu,Th on DIRN */ MuxA = (Sel : 'd'0) & Q0_a # (Sel : 'd'1) & Q1_a # (Sel : 'd'2) & Q2_a ;and CUPL allows you to create Test Vectors, so if you have a Device Programmer, you can test a device before dropping it into a board.
Example of Test Vectors : ======================== I CC l LL l KK e C O QQ __ g QQ L E ii DU a ff K N ba nn l ba ======================== Power on checks, RSTN to 0000 ? 0001: 0 0 11 HH L HH 0002: C 0 11 HH L HH 0003: C 0 11 HH L HH Check single impulse L 0004: C 0 01 LH L HH 0005: C 0 11 HH L LH 0006: C 0 11 HL L LH 0007: C 0 11 HH L HHThis should be quite workable.
There is a "loophole" in the radio emission specks. If the clock frequency is 9.6KHz or less no testing is required.
EMI testing costs at least $10,000us to do.
So, it would seem to me, that for each CPLD clock a new state change is performed.
It may take 10s to 100s of clocks for a micro to do the same thing.
Am I fundamentally wrong about this?
Obviously, a micro is programmable and far more versatile.
But the CPLD can do low level logic functions quite well and not require testing.
I hope this is possible. What do you think?
I'm presently using a CMOS 2Kx8bit static EEPROM CAT28C16A. I made a simple Prop on a plugboard to program it. I just download an image to FemtoBasic which does the programming.
It would be cool if I could do something similar to the ATF750LVC.
What do you think?
Duane J
Correct.
It's not clear exactly what you intend ?
The small PLDs are well suited to slave IO, and they cannot 'hang' like a CPU can.
The limit tends to be the number of macrocells.
take a normal Spec ani and a RF tight box . put the DUT the box and see what trash the DUT puts out ... I did this for all my home brew ham gear . I used a all metal tool box and some RFI mesh gaskits .. was worked well and was simple .
not ANSI or NIST for shure but I cant for the life of me see what is so costly ......
i was looking for cpld i guess. the chips that let you draw logic blocks and can be programmed in verilog/vhdl the whole point being was to take a good first step twords fpgas.
something like this is what id planned on buying its cheap and my bus pirate can program it
http://dangerousprototypes.com/docs/CPLD:_Complex_programmable_logic_devices
so is thete something in a dip package that i can use to learn the "hardware languages"? i dont have anything specific in mind as far as capabilities besides being able to latch 8 or 16 spi srams to a prop, after i know what im doing
Nope, the nearest would be the breakout boards/eval boards from Lattice Semi, for their MachXO2 and SiliconBlue parts.
Those have 0.1" IO grids, but all parts in that class, are TQFP/BGA/QFN.
I want something thats in a dip package I can easily use in projects without a dev board, but I also have the feeling if I dont pic up something like the basic stamp of programmable logic I wont get far at all, thats why I was really intrested in the visual layout program like in the quartus software. If I understand correctly all the vhdl/verilog stuff out there will work as long as the chip your using has the power and logic cells
The code is Atmel CUPL, which is lower level than Verilog, and much faster to compile than Verilog et al.
The larger chips support Verilog, where it makes more sense, but I'm not sure you _need_ verilog to implement a few 7400 chips - at that level, you will be writing boolean equations in verilog anyway.
You can use DIP, but you do need a Device Programmer.
Drop programmer ATF16V8B into eBay, and you get some idea of prices.
The better ones support Vector Testing.
Once you jump to JTAG, you also jump to PLCC/tqfp.
Verilog is not a visual layout entry, it is simply source code/text file, like any HLL.
In my former life at Unisys we did this testing on computers and other hardware we sold.
OK, some of this was rather large and cost many times $10,000.
For small equipment it just always hovered around 10 grand + -.
This testing is done at what is called an "Open Field Test Site". Basically a location remote from interfering radio noise. Generally they have a rotating turntable where the equipment is placed. Antennas are located 10m away with receivers one level below, usually underground.
Guys scan the spectrum from 10KHz to 10GHz and note every signal, (there are a lot of them). The signal list is weeded out so only the ones from the equipment are scanned. The turntable is rotated and antenna height varied to maximize each signal.
Anyway, this testing is quite expensive. The least expensive I ever heard about was around $6,000 but this was battery powered and had no external connections so there was just nothing to read.
You can test strictly to the FCC specs, (US only), but most also test to the TUV specs so the stuff can be sold world wide. As an example look at almost anything electronic. See the FCC or TUV sticker on it. I've been out of the business for 7 years so I wouldn't be surprised if the costs are even higher.
My goal was to devise electronic solutions the didn't need to go through the hassle of EMI testing. Generally analog or slow clocked digital circuits don't need to be tested. Note, switching power supplies must be tested.
I'm interested in the CPLD as it looks like it might work nicely. I am now using CMOS EEPROMs as logic elements but they are quite limited in what can be done. Years ago I tried GALs but that was quite power hungry.
Duane J
If power comsumption is to be concerned and comparing the ON Semi EEPROM and the Atmel CPLD @ 5V supply, the CPLD will use at least twice the current. When Inputs/Outputs are changing states or the CPLD being clocked (may be internaly changing states, but no change in the I/Os due to signal routing) things can get even worse.
Also the EEPROM can be put in a Standby (-CE controlled) mode that uses even less power.
Due to the low propagation times of the product terms of the CPLD and the complexity of the programmed function they will exhibit bursts of RF rich noyse anytime a change occurs in the Input or I/O pins connected to the logic equation one programmed it to do.
Yanomani
I'm quite aware of the differences in power dissipation.
The 2Kx8 EEPROM has severe limitations on what can be done.
The CPLD appears to be much more versatile in what it can do, I can take the power hit.
Of course the faster rise times cause high order harmonics. The power bandwidth of the harmonics is directly proportional to the clock frequency. Actually, as I recall, the power bandwidth may be approximately proportional to the square of the clock frequency. So low clock frequencies don't produce very much interference.
Anyway, it's their rules. Less than 9.6KHz and they don't care so no testing is required.
Of course prudent circuit design and packaging should always be done.
Note!! Loophole or not, even if a device is certified yet it still interferes with a higher priority communication service one must cease and desist and stop interfering. Even if it has the TUV or FCC sticker. Again their rules.
Duane J
http://www.seeedstudio.com/depot/xc9572xl-cpld-development-board-v1b-p-799.html?cPath=174
.
And at the bottom of the that page there are links to CPLD resources and tutorials. It's worth a look.
What Logic do you put into the 2Kx8 EEPROM ? - Do you use an external register, for state-engine address feedback ?
The FRAM variants are edge activated, (ie include a latch) so they can be used in simple state engines, and at low clock speeds you will be clear of any lifetime issues.
Examples might be FM16W08 (8kx8), and MB85R256F (32Kx8) and I see the MB85R256F has a max low time on CE of 500ns (min of 70ns)
For wide supply and lowest Icc the Atmel ATF22LV10CQZ works well for 24 pin tasks, and the ATF1504ASVL covers 44 pin tasks.
The ATF750CL has << 1mA Icc and 20 macrocells, so can replace a 22V10, but usually we jump to the ATF1504ASVL.
I also use the ATF16V8BQL, which has under 2mA Icc and vector tests down to 2.4v, for the cheapest moderate power device.
You can do small ROMs like 7 segment displays, or counters, in a SPLD/CPLD.
The pivot question here, is do you already have a Device Programmer that supports the Atmel SPLDs ?
If yes, you simply buy the parts and download the SW.
If not, you will need to buy/borrow one .
They tend to come in two levels, ZIF40 and ZIF48, with some of the better ZIF48 models able to pgm and Vector test the PLCC44 parts as well as DIP20/DIP24
Of course - they ALL have Flipflops and Combinatorial logic - all that changes is the mix and shuffle of these.
The post-fit reports from your Verilog, will also be in Boolean equation form, so being able to read that is useful.
CUPL has TTL macros, some examples
Things like AND/OR/XOR they usually do not bother with macros, as that's just & # $
Even for the above macros, you may decide it is clearer/easier to simply code what you want, than include a Macro call.
This was for a specialized dual axis solar tracker with limit switches, motors, and 2 tracker circuits. This thing got fairly complicated. I breadboarded it with 9 16 pin logic gates. The board area was getting a bit large in area. So I used the 2Kx8 EEPROM CAT28C16A which was much smaller.
I had made some EPROM state machines in the early '90s with good success. But kind of moved away from that path.
I think I want to try some of the ATF750LVC parts and see how they work.
It would be nice if I can program them with a dedicated Prop. What do you think?
Duane J
I have a bunch 74xx chips but this seems like a much cleaner and easier path to learn digital logic, and cheaper as you dont have to buy all the 74xx chips and hook up wire. My end goal is to use 8 to 32 (32 is probably shooting for the stars I know but that means one long from sram could be read in parallel by the prop) of microchips 1Mbit quad spi sram chips and interface it to a propeller as fast as possible with as little pins as possible.
If I feed programmer ATF16V8BQL and tick eBay's include description, then I get 15 hits, ranging in price from $99 to $59
The more generic programmer GAL16V8 gives 40 hits
The one I use here is
http://eetools.com/index.cfm?fuseaction=product.display&product_ID=303&ParentCat=17
but I am interested in finding a lower price SPLD device programmer.
There is a range showing here :
http://www.goodluckbuy.com/electronics/programmer-and-socket.html
Summary: You will need a Device Programmer (ZIF) box of some sort, to pgm SPLDs.
If you type programmer CPLD then you open the many JTAG clones, and the Atmel ISP Sw can support some Altera Byteblaster variants.
There are also some break-out boards, so that is a worthwhile search.
Programming these is non-trivial, you need Vpp and some Vcc control, as well as multiple pin-wiggling.
So that moves them outside host programming.
We are researching a form of ISP, where the idea is to 'top-hat' clip over a SMD mounted PLCC package, and provided the target has pin3 Vpp compliant, and can allow drive to IP pins, then you could re-flash a mounted device
Sadly, no one thought to make these i2c or similar, as PLDs started needing complex fuse programmers, and then tended to drag that legacy with them.
The JTAG ones might manage Host programming, and I've seen some code for that - the HW is just SPI, so the problem is purely SW.
Even there, that is not small (32K binary from memory?) and you still need to get the JED fuse info to the target somehow.
I've only seen that done for extreme instances, like a sealed case where they might want to update the CPLD.
JTAG from a PC is cheap, from $10 to $50..
Another pathway would be to use SVF, which is a sort of JTAG script.
I found this
http://www.embeddedcomputers.net/products/FlashcatUSB/
If I take a CPLD source file here, the Binary fuse image is 2100.75 Bytes, and that is contained in a 19,610 byte .JED file, and the Atmel tools can create a 85,436 byte .SVF file, and the SVF is 4131 lines of code like
- and a 'svf player' that reads that spagetti, and wiggles the JTAG pins, would be possible, but would use ?? of a Prop ?
In my modest opinion the XC9572XL can be a better choice. If you can work with its SMD profile it seems to be easily in circuit programmable and also costs less than the ATF750LVC.
Yanomani
If you go with Altera you can use their schematic entry tools and place a decade counter or what ever is available in the 74xx series in your CPLD with just a few mouse clicks. Mind you there is a learning curve to use these tools - but they come with video files to help you.
I also am not yet familiar with these items as the last project I did with programmable logic used the MMI series PAL chips, and before that PLAs which I had to have programmed for me by the distributor, avnet or similar. I think I finally lost or tossed the programmer for them (PALs) a few years and moves ago. Probably lost. Anyway, if you need a good source to start with learning digital logic and perhaps state machines, look into a book called "Digital Logic and State Machine Design"" by David J. Comer. Gets in some very good material. I don't know how much optimization the new compilers will do and how much is left up to you, so parts covering boolean algebra may also be useful to you.
In my former life at Unisys we did this testing on computers and other hardware we sold.
OK, some of this was rather large and cost many times $10,000.
For small equipment it just always hovered around 10 grand + -.
exactly , some one is paying for papers to be "Stapled " . Its not like you need 20 EEs to test a Ipod
I guess cause some one can charge for it they do
On that note we have a TON of people here doing stuff with chips that clearly are over 9 K . so how are WE not in jail ?
I mean a slow digital here is one way but how is that going to be applyed to others who need fast IOs .
all the hams that sell pre made radios are I guess in for it .