While searching for more info I ran across this informative link. An Overview of Sigma-Delta Converters It got me wondering if I could make a 2nd order sigma-delta modulator with the Propeller?
Lawson
Thanks for that link BTW. I saw that the author of the article has a well-regarded book, Understanding Digital Signal Processing now with a 2011 3rd edition. From the reviews and the "look inside", it does look good, and practical.
"On the input side, you do not need a comparator, you can use a fast OpAmp as the true integrator instead."
1) No comparator? The accuracy or at least the stability of the quantizer is of paramount importance. The Propeller threshold is not symmetrical, it drifts with time and temperature, and there is the underlying noise issue. Are you qualifying that by "on the input side"? What is being integrated is usually linear combination of the input signal and the digital feedback.
See the Spice plots, a picture is worth 1000 words.
The difference is the slew rate. With the approximate integrate, you need a large Tau, relative to clock, and that gives very low amplitude modulation, which makes the reference (threshold) noise very important.
With a true integrate, the slew rate is far higher, and so the threshold variations are (greatly) attenuated
You could add a Comparator, but once the slew changes are done, I put this in the diminishing returns basket.
See the Zoom capture (R7=0,001). (note this is at 10MHz, so x8 on 'std' prop dV and also Rf is lower, so a ~x53 total 'std'. dV)
{As R7 increases, you can force more amplitude (but a similar slew rate). Not sure how that would resolve in a real ckt.}
At more typical Prop R/C/f values, (120K/2n/80MHz) you have in the region of 100uV/Clk of sawtooth at the D-FF threshold, whilst an integrator is around 5000x that.
It is amazing the prop ADCs work as well as they do.
2) True integrator? The capacitor*2 in the standard propeller circuit is I think operating pretty close to being a true integrator. To first order the dV/dt ramps at the summing junction are linear, and the summing junction voltage is constant just as you have in an op-amp integrator.
The instinctive issue I have with a primitive RC, is charge leakage.
You are trying to sum charge, over long times, but the e-t/tau effect says the memory of that charge is hazy.
A true integrate avoids that, and also gives the benefit of far higher dV/dT at the D-FF pin.
Spice confirms this instinct, but only partially. The effect seems more 'sudden' than my instincts suggest.
Below a critical CAP value, ( less and less Tau) spice shows the RC 'integrate' does indeed loose LSB resolve.
Two parallel running instances with a small % offset, simply 'snap'.
- but above that Tau value, it seems to not improve slowly, but rather more quickly.
Of course this type of difference test pushes Spice.
Okay, thanks for the explanation. I was thinking of something more prop-centric. Maybe the prop could drive the clock (V1) and read the Q2\. The input signal is V2. The D-FF labeled A1 is not doing anything important, is it? You mention R7 prominently though in your explanation--maybe that is a typo.
Okay, thanks for the explanation. I was thinking of something more prop-centric. Maybe the prop could drive the clock (V1) and read the Q2\. The input signal is V2.
Yes, you can use a external D-FF, either with, or without an integrator.
If you use it without, you effectively clone the Prop's buried D-FF, but it buys you some power supply isolation.
If you omit the integrator, you still have an issue that the very small sawtooth, makes the D-FF threshold very important.
Not all logic likes linear biasing, and some will Oscillate internally at linear bias points. That would mess with the noise floor.
A simple Buffer/SPCO switch will isolate the digital rails of the chip, but still use the Prop D-FF threshold - this buffer should have matched Tplh,Tphl.
The D-FF labeled A1 is not doing anything important, is it? You mention R7 prominently though in your explanation--maybe that is a typo.
A1 is wired as a Prop equivalent, so I can see both running. It is not important for the integrator ADC, which uses A2.
R6,R7 are an experimental means to lower the decision frequency, and increase the slew on the D-FF, by injecting a small positive feedback signal. Not sure if that will buy you anything in a prop, in noise floor terms ?
How about pipelining the samples? That is what is done I believe in some of the so-called low latency sigma delta converters. Instead of strictly sequential samples, C1, C2, C3,..., overlap them like in the diagram, s1,s2,s3,... still the same total counting interval. Samples are taken at interval z and add to N sub-accumulators. Each sample when complete can feed into the CIC triple integrator and decimator.
The sub-accumulators would be easy to implement as a circular buffer. Just add the new sample to the total and subtract the entry that it replaces in the buffer. Basically, you end up with a boxcar averaging scheme, which is a special case of a FIR filter.
Ah! yes, equivalent to a boxcar, recursive moving average. In the article that Lawson referenced and implemented, that is expanded to three cascaded accumulators (integrators) followed by 3 decimators (the comb). One problem was the issue of overflow, because the accumulations can become very large and overflow 32 bits. But it is just additions and shifts, so even with 64 bits it should be doable. I was just wondering if there would be any advantage to producing the samples that go into the CIC section at a faster rate, overlapping instead of successive. That is, a boxcar to precede the CIC.
That's getting close in price to a better class of opamp, and this has a Bridge PGA and Step programmable LDO as well.
It can also provide a good means to performance check any 'Prop-only' ADC designs
NAU7802
Supply power: 2.7V~5.5V
On-chip VDDA regulator for internal analog circuit or external load cell
Programmable VDDA: Off, 2.4V to 4.5V with eight options
Minimum 10mA output drive capability at 3.0V output voltage
Note: DVDD must be 0.3Vdc greater than desired VDDA output voltage
One way of improving the noise performance of CMOS digital inputs used as comparators is to add some gain as a front-end.
A single-transistor fixed gain stage would trade off some drift+offset for a much lower noise. It would also remove the need for a VCC-referenced integration capacitor.
I'd guess that 2 jellybean BJT transistor pairs that cost pennies might improve things significantly. One could do a current source (turned bipolar with a pull-up resistor), another could act as a differential gain stage to the comparator. I've played with such circuits in the days where 12 bit 8-pin PIC chips were hot potatoes, and 16 bit resolution with 32LSB INL was typical performance (slow of course). The PIC was a glorified counter while the conversion took place. That was eons ago - I'd have to try it out later today!
Comments
Thanks for that link BTW. I saw that the author of the article has a well-regarded book, Understanding Digital Signal Processing now with a 2011 3rd edition. From the reviews and the "look inside", it does look good, and practical.
See the Spice plots, a picture is worth 1000 words.
The difference is the slew rate. With the approximate integrate, you need a large Tau, relative to clock, and that gives very low amplitude modulation, which makes the reference (threshold) noise very important.
With a true integrate, the slew rate is far higher, and so the threshold variations are (greatly) attenuated
You could add a Comparator, but once the slew changes are done, I put this in the diminishing returns basket.
See the Zoom capture (R7=0,001). (note this is at 10MHz, so x8 on 'std' prop dV and also Rf is lower, so a ~x53 total 'std'. dV)
{As R7 increases, you can force more amplitude (but a similar slew rate). Not sure how that would resolve in a real ckt.}
At more typical Prop R/C/f values, (120K/2n/80MHz) you have in the region of 100uV/Clk of sawtooth at the D-FF threshold, whilst an integrator is around 5000x that.
It is amazing the prop ADCs work as well as they do.
The instinctive issue I have with a primitive RC, is charge leakage.
You are trying to sum charge, over long times, but the e-t/tau effect says the memory of that charge is hazy.
A true integrate avoids that, and also gives the benefit of far higher dV/dT at the D-FF pin.
Spice confirms this instinct, but only partially. The effect seems more 'sudden' than my instincts suggest.
Below a critical CAP value, ( less and less Tau) spice shows the RC 'integrate' does indeed loose LSB resolve.
Two parallel running instances with a small % offset, simply 'snap'.
- but above that Tau value, it seems to not improve slowly, but rather more quickly.
Of course this type of difference test pushes Spice.
Yes, you can use a external D-FF, either with, or without an integrator.
If you use it without, you effectively clone the Prop's buried D-FF, but it buys you some power supply isolation.
If you omit the integrator, you still have an issue that the very small sawtooth, makes the D-FF threshold very important.
Not all logic likes linear biasing, and some will Oscillate internally at linear bias points. That would mess with the noise floor.
A simple Buffer/SPCO switch will isolate the digital rails of the chip, but still use the Prop D-FF threshold - this buffer should have matched Tplh,Tphl.
A1 is wired as a Prop equivalent, so I can see both running. It is not important for the integrator ADC, which uses A2.
R6,R7 are an experimental means to lower the decision frequency, and increase the slew on the D-FF, by injecting a small positive feedback signal. Not sure if that will buy you anything in a prop, in noise floor terms ?
-Phil
This is a 16 Pin SO (or DIP) 24b ADC converter.
http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=959b12f1-27f0-4108-9cfd-463de479a0cc
That's getting close in price to a better class of opamp, and this has a Bridge PGA and Step programmable LDO as well.
It can also provide a good means to performance check any 'Prop-only' ADC designs
NAU7802
Supply power: 2.7V~5.5V
On-chip VDDA regulator for internal analog circuit or external load cell
Programmable VDDA: Off, 2.4V to 4.5V with eight options
Minimum 10mA output drive capability at 3.0V output voltage
Note: DVDD must be 0.3Vdc greater than desired VDDA output voltage
23 bits effective precision analog-to-digital converter
Simultaneous 50Hz and 60Hz rejection (reaching -90dB)
RMS Noise:
50nV in 10 SPS data output rate and PGA gain = 128
150nV in 80 SPS data output rate and PGA gain = 128
Programmable PGA gains from 1 to 128
Programmable ADC data output rates
External differential reference voltage range from 0.1V to 5V
One way of improving the noise performance of CMOS digital inputs used as comparators is to add some gain as a front-end.
A single-transistor fixed gain stage would trade off some drift+offset for a much lower noise. It would also remove the need for a VCC-referenced integration capacitor.
I'd guess that 2 jellybean BJT transistor pairs that cost pennies might improve things significantly. One could do a current source (turned bipolar with a pull-up resistor), another could act as a differential gain stage to the comparator. I've played with such circuits in the days where 12 bit 8-pin PIC chips were hot potatoes, and 16 bit resolution with 32LSB INL was typical performance (slow of course). The PIC was a glorified counter while the conversion took place. That was eons ago - I'd have to try it out later today!