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High Precision Propeller Sigma Delta ADC? — Parallax Forums

High Precision Propeller Sigma Delta ADC?

LawsonLawson Posts: 870
edited 2012-09-03 20:38 in Propeller 1
I've been playing around with the Sigma Delta ADC circuit on the quickstart. Having a lot more success using a known good layout and component values for this round of experimentation. My goal is to get the best precision I can with a 10-30Hz sample rate. So far I can get about 13-14 stable bits. Super sampling followed by a CIC averaging filter hasn't shown a significant improvement. (though it likely rejects aliasing better)

While searching for more info I ran across this informative link. An Overview of Sigma-Delta Converters It got me wondering if I could make a 2nd order sigma-delta modulator with the Propeller? Page 14 of the link has a section on higher order sigma-delta modulators. Several of modulators discussed look like they could be implemented with an expanded RC input network and or by pairing two counters. (might this be a use for the POSEDGE W/ Feedback counter mode? i.e. Figure 17)

Lawson
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Comments

  • jmgjmg Posts: 14,847
    edited 2012-08-20 21:53
    The classic Sigma-delta uses a OpAmp as an integrator, and a D-FF.
    A true integrator properly accumulates charge, which a RC filter does not.

    So you could build one of those, as a reality check and Clock/total in the Prop.
    The external D-FF will remove power supply noise issues, and the Clock choices will allow you to find the best CLK rate.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-21 09:51
    Hi Lawson,

    I've wondered too about making a second order response.

    However, the layout-related noise floor is going to have to be pushed down. The Quickstart sigma-delta demo pads are a compromise with the versatility that was its main design goal. A closeup of the layout is attached, with the components in red that have to be added to implement the sigma delta.

    I circled the points where logical pins 8 and 9 (physical pins 9 and 10) connect via long traces to the prototyping area. Start by cutting those (drill bit in the holes), to eliminate their parasitics.

    The layout is good in the sense that it uses logical pins p8 and p9, which have short internal connections to COG0. (reference) The input and feedback connections are tight. On the other hand, the integration capacitor C0 and the power bypass capacitors both connect to a ground node that is on a narrow neck that has a long path back to the Vss pin on Prop pin 5. C1 has a short path back to Vdd on pin 8, but the Vdd distribution bus itself is made of narrow high inductance traces. The summing junction is crossed by the signal paths to and from the FTDI serial port in a way that would allow pF's of coupling.

    Let's think about a board layout specifically optimized for achieving the best possible noise floor from the Prop 1. A four-layer board with nearly solid power and ground planes could be the best bet for low noise and low impedance path to the power supplies.

    quicstart_sigdel_layout.png
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  • LawsonLawson Posts: 870
    edited 2012-08-21 23:13
    @Tracy: I think you're on to something. I've slowed my code down to 5MHz (to save power) but still sample at 19Hz. The data so far looks like I'm getting 14 stable bits. So 1/16th the sample rate, and the noise is the same or better. Sounds like a clue that the modulator or sampling noise isn't the limit.

    Lawson
  • jmgjmg Posts: 14,847
    edited 2012-08-21 23:44
    Lawson wrote: »
    I've slowed my code down to 5MHz (to save power) but still sample at 19Hz. The data so far looks like I'm getting 14 stable bits. So 1/16th the sample rate, and the noise is the same or better.

    In theory, you could get 14 bits from a 19Hz sample rate, and a 311,296 Clock, so you could go even lower.
    In a bare Prop circuit, I would expect power/ground/threshold noise to largely set noise floors.

    Hence my suggestion in #2 to use an external real Integrator, and D-FF
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-22 10:57
    jmg, I'd like to hear more specifically what external circuit, with the Prop in the loop, you would use to achieve either first or second order. I recoil at the added complexity, and I'm with Lawson and would rather first pursue the limits with the prop1 solo. (and wait for the Prop2 with its tight internal ADC)

    External components face the same issues. If the target happens to be accuracy as well as precision, that will call for a high speed comparator rather than just a D-FF or logic gate, and in any case the components operate near their switching thresholds with huge potential for ground bounce and oscillations.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-22 11:15
    When you look at the summing junction for the sigma-delta on a high speed 'scope, it is not a neat, clean integration. There is also superimposed ringing, which I surmise comes from resonances in the power supply as it bounces from the switching transients. If both supplies happen to bounce in phase, then it should make less difference, given the double integration capacitor. However the power supplies are not identical at high frequencies. I'm talking specifically about the quickstart sigma delta demo circuit. It is pretty good, but like I said before, it is a two layer board and had to compromise for versatility.

    I took a stab at how I would lay it out on a 4-layer design. This also uses p8 and p9. The blue and orange crosses indicate thermals on the ground and Vdd power planes. CB and Cb are bypass caps. This is a QFN and their would also be vias from the center pad to the ground plane. Comments?

    sigDel4layout.png
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  • LawsonLawson Posts: 870
    edited 2012-08-22 12:24
    When you look at the summing junction for the sigma-delta on a high speed 'scope, it is not a neat, clean integration. There is also superimposed ringing, which I surmise comes from resonances in the power supply as it bounces from the switching transients. If both supplies happen to bounce in phase, then it should make less difference, given the double integration capacitor. However the power supplies are not identical at high frequencies. I'm talking specifically about the quickstart sigma delta demo circuit. It is pretty good, but like I said before, it is a two layer board and had to compromise for versatility.

    I took a stab at how I would lay it out on a 4-layer design. This also uses p8 and p9. The blue and orange crosses indicate thermals on the ground and Vdd power planes. CB and Cb are bypass caps. This is a QFN and their would also be vias from the center pad to the ground plane. Comments?

    sigDel4layout.png

    First a comment on the ringing. Did you use the 3-4 inch ground lead on the scope probe, or make a direct ground connection from the tip of the probe to a point millimeters from where you are probing? I've seen the ground wire on probes ring way too often to blame the circuit first.

    On the layout, I'd also suggest making a "jumper" footprint for passives 0603 or larger. My "jumper" footprint has a 0.030 inch gap (or more) between the pads and I make sure this gap lines up with the routing grid. (easiest if the footprint origin is centered on the gap) This footprint helps a LOT with packing a tight layout onto 1-2 layers because signals can escape below any passives.

    I've Also had VERY good luck with my designs when I use a ground layer and nearly 1-layer routing. My most recent success is with a GHz comparitor and flip-flop. (the signals are probably clean, but I used a long ground lead so I'm not sure) Because of this, I'd personally try a 2-layer design first. Not the easiest thing near a Propeller though, as it's always in the center of any tangled schematic.

    Lawson
  • jmgjmg Posts: 14,847
    edited 2012-08-22 15:46
    jmg, I'd like to hear more specifically what external circuit, with the Prop in the loop, you would use to achieve either first or second order. I recoil at the added complexity, and I'm with Lawson and would rather first pursue the limits with the prop1 solo. (and wait for the Prop2 with its tight internal ADC)

    External components face the same issues. If the target happens to be accuracy as well as precision, that will call for a high speed comparator rather than just a D-FF or logic gate, and in any case the components operate near their switching thresholds with huge potential for ground bounce and oscillations.

    A bare Prop gives quite good results, given how it works - but there are a lot more cross talk issues with a prop die, than with a single D-FF externally. Precision will change with what else the Prop is doing at the time..

    The external D-FF effectively allows switching to a clean Vref/Gnd, and I've seen this used to calibrate and noise test 24 bit ADCs.

    The next weak-point in a Prop Quasi-ADC, is the RC used is not a true integrator - the time constant means it leaks LSBs, so a better integrator is needed if you want better precision.

    A middle-ground solution, could use the D-FF in the Prop, but an external Vref/Gnd switch, and an external integrator, and be CLK varied for best LSB.

    Of course, with external parts, you do need to keep an eye on design time, measuring time, and the alternatives like

    http://www.ti.com/product/msp430afe221

    which give you a configurable 24 bit ADC for a couple of dollars.

    There are a growing number of Metering front ends being offered, such as this

    http://www.maxim-ic.com/datasheet/index.mvp/id/7786
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-22 16:13
    'scope: I was indeed touching the ground barrels (no long clips) to a heavy wire sticking up from the sigma-delta input ground connection. But... it was a precarious situation with two probes hand-held, one to the feedback output and one to the sense input. If I get a chance, I'll revisit it to try to narrow down the source vs the artifacts.

    I did that layout with 0402 resistors, but truth be told I'm more comfortable too with 0603s for protos and test. Alternate layout using 0603s below. As before, the orange X indicates a connection to a Vss power plane (4-layer board). However, this does have room between the pads to carry a Vdd power trace out to the left if is converted to a two layer design. I know what you mean about minimizing the number of traces on the bottom and using a large practically unbroken ground plane there. I recommend that too. The nice thing about the Prop is the interchangeability of most of the pins, which eases the routing requirements so that more can be done without jumping layers. However, the two layer board with the big ground plane leaves you with high inductance Vdd routing. The quickstart has neither a solid ground pour nor a low inductance power feed. I'm just curious if a demonstratively better noise floor could be had with 4-layers.

    sigDel_4layout_0603.png
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  • LawsonLawson Posts: 870
    edited 2012-08-22 21:17
    @Tracy: Glad to see my scope comment was redundant. I'd expect a heavy wire sticking up to touch the probe ground ring near the tip to be plenty. (though if you have a GHz scope I bet it would still ring or distort some at the highest scan speeds.)
    However, the two layer board with the big ground plane leaves you with high inductance Vdd routing.
    Figured the bypassing capacitors on a board evened out the impedance of Vdd vs Vss? Would make sense that an actual power plane would be better. And since good 4-layer prototype options exist, I'll stop complaining :)

    @jmg: A D-flip flop powered off a reference and wired to do delta-sigma like the propeller is as precise as a commercial ADC? I'll have to try that! Even if it's slow, that's a useful trick for it's cost/precision. If you only added an op-amp integrator or an external ref/ground switch to the Propeller sigma delta circuit, which do you think would help the most?

    That MSP430 sure looks nice. (f'n cheap too!) Can't find any noise/precision specifications for it's ADC's though. (I expect the specs are bad if they don't make it into the datasheet.) I've also been looking at the MSP430's a bit for very simple low power applications. Though the 220uA/1MHz boast in MSP430 data-sheet doesn't look so impressive after looking at the Propeller's power consumption. (with 8 cores running spin the Prop matches that slope)

    Lawson
  • jmgjmg Posts: 14,847
    edited 2012-08-22 21:54
    Lawson wrote: »
    @jmg: A D-flip flop powered off a reference and wired to do delta-sigma like the propeller is as precise as a commercial ADC? I'll have to try that! Even if it's slow, that's a useful trick for it's cost/precision.

    You would need a D-FF and an Integrator for the best results.

    Lawson wrote:
    If you only added an op-amp integrator or an external ref/ground switch to the Propeller sigma delta circuit, which do you think would help the most?

    You would be best to start with both, and then measure, removing one.
    The external switch benefit tests would depend on what else the Prop was doing.
    All Gogs running tasks, will produce more crosstalk and bounce.

    An external integrator I would expect to need a lower clock speed for best precision, but that is easy to trial.

    At 19Hz you have some in reserve - 5MHz would indicate ~18 bits.
    An opamp like an OPA354 or OPA356 would be a starting point.

    Low Ib is important for an integrator, and good slew rate means you can run a higher clock, and low noise is always good.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-23 12:10
    Easier said than done. The number of variables to experiment with increases exponentially when more external parts are added, especially in a layout-critical high speed circuit like this. Even with the basic circuit there are plenty of questions about the choice of components, for example, the still unanswered questions about the choice of capacitors and effects of capacitor ESR. The bias conditions on the other hand are well understood.

    My interest for this is for higher speed stuff that has less need for DC stability, for example from vibration (audio) transducers or photodiodes, and it is for that I'd like to push the limits of the noise floor. My intention is to make a few of the 4-layer boards from dorkbotpdx and see if there is any improvement and to have a platform to experiment with the component values. I'm thinking now I should use p8 and p10 and leave p9 for crosstalk isolation. So many variables!

    I don't have any problem with adding external components, but I think they should best serve a support role. For DC precision/accuracy I always reach for the easy to use integrated chips, like the Burr-Brown/TI ADS11xx series of 16 bit sigma delta converters.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-23 12:13
    Lawson, even though it didn't give the improvement you expected, how did you implement the "super sampling" followed by the CIC averaging filter?
  • LawsonLawson Posts: 870
    edited 2012-08-23 13:31
    Lawson, even though it didn't give the improvement you expected, how did you implement the "super sampling" followed by the CIC averaging filter?

    I made the CIC filter following This link. I've attached the two files I used to test if a CIC filter had anything to offer. The first file is fixed at a 3rd order CIC, while the second file will do a settable order CIC. With both, you need to be careful not to overflow a 32-bit word size. (I also run a simple average filter in parallel in this code for comparison)

    The Key code is
    'CIC accumulator stages
        CICacc[0] += super
        CICacc[1] += CICacc[0]
        CICacc[2] += CICacc[1]
    
    Run for every raw/quick sample taken
    and
    'CIC comb stages
      temp := CICacc[2] - CICdiff[2]                        'subtrace off old value
      CICdiff[2] := CICacc[2]                               'update old value
      temp2 := temp - CICdiff[1]
      CICdiff[1] := temp
      temp := temp2 - CICdiff[0]
      CICdiff[0] := temp2
      SDvalue := temp >> (CIC_order * divide_bits + Aquire_bits - output_bits)
    
    Which takes the differences and needs to run once for every processed/slow sample produced.

    I may go back to super-sampling with a CIC if I find problems with low frequency aliasing.
    jmg wrote:
    At 19Hz you have some in reserve - 5MHz would indicate ~18 bits.
    My understanding of the modulator noise is that I'll never have 18 stable bits if I accumulate for 2^18 clock periods with a first order modulator. (right now I get ~14-bits stable and ~16-bits rms with 2^18 clock cycles accumulated. at 5MHz)

    Lawson
  • jmgjmg Posts: 14,847
    edited 2012-08-23 13:39
    Lawson wrote: »
    My understanding of the modulator noise is that I'll never have 18 stable bits if I accumulate for 2^18 clock periods with a first order modulator. (right now I get ~14-bits stable and ~16-bits rms with 2^18 clock cycles accumulated. at 5MHz)

    Without a proper integrator you will not get 18 bits - and even 14 bits with a simple RC design is good.
    Is that with anything else running in the test system ?

    With a proper integrator and digital crosstalk issues removed, it is a variant on proper dual-slope ADC, and so 18+ bits should be possible.
  • LawsonLawson Posts: 870
    edited 2012-08-23 13:48
    At the moment I'm only running a serial port in addition to the ADC code. Eventually, I'll also have a sound effect triggered periodically by the ADC.

    Lawson
  • LawsonLawson Posts: 870
    edited 2012-08-24 18:55
    Another note. Turning on the PLL and running with a 10MHz clock and 19Hz sample rate has 1.5-2x the noise of running without the PLL at 5MHz. This would indicate that using a fast crystal and no PLL is best for sigma delta precision.

    Lawson
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-24 21:08
    In that case, how about 12MHz RCfast? The conversion is ratiometric, so the exact clock speed does not matter, to first order.

    Midrange PICs can execute a SLEEP instruction to quiet the processor clock while the AD conversion (SAR) uses its own RC clock, and end-of-conversion wakes the processor. The Prop couldn't do exactly that, but no matter what the clock source, other i/o activity could be coordinated, or cogs put in a wait state.
  • jmgjmg Posts: 14,847
    edited 2012-08-24 21:51
    Lawson wrote: »
    Another note. Turning on the PLL and running with a 10MHz clock and 19Hz sample rate has 1.5-2x the noise of running without the PLL at 5MHz. This would indicate that using a fast crystal and no PLL is best for sigma delta precision.

    Could have been jitter, or just more digital activity ? That's why tests should have 'typical' code operating.
  • jmgjmg Posts: 14,847
    edited 2012-08-24 21:53
    In that case, how about 12MHz RCfast? The conversion is ratiometric, so the exact clock speed does not matter, to first order.

    Easy enough to check - however, I would expect any RC osc to be rather worse, as the underlying assumption is of precisely EQUAL time slices. Absolute frequency is not so important, but jitter and stability are.
  • jmgjmg Posts: 14,847
    edited 2012-08-24 22:12
    I'm just curious if a demonstratively better noise floor could be had with 4-layers.

    If you want to build a 4 layer test bench that is purely Prop-engined, I can think of a couple of test items to add to a layout.

    a) an option to bias the charge caps, C0,C1 to prop pins, which are then pulled HI and LO.

    These will give local-power-levels, as they will come from the supply rails nearest to the Pin Buffer.

    b) You can lower the equivalent SDM sample rate, but still have a high clock, by using a divider from Q to inject a few hundred mV of positive feedback to the Charge cap cold ends. ( Negative Feedback is from QN ).

    c) Working on the idea that jitter and noise to some moderate precision are unavoidable, you can add parts that deliberately sweep the operating point over a few tens of mV.

    One way to do this, is a NCO divider, that is aggressively filtered to give a low amplitude triangle wave. (50mV-150mV?)

    This lets you easily adjust the sweep, and total sum times should be locked to a whole multiple of these sweeps.
    eg a modulate rate of 512 samples, would average over 512 modulate cycles, to give 2^18 totals.
    (or a modulate of 1024 samples, averaged over 256 full modulate cycles, is similar )

    d) an option for a 1G Logic buffer, to clean AV+, AV- supply rails. This should be a fast, low skew part if it is not to degrade the balance.
    Yes, this is not quite pure prop, but it does allow a measurement on the supply-contribution to noise floors.
  • LawsonLawson Posts: 870
    edited 2012-08-25 08:43
    jmg wrote: »
    Easy enough to check - however, I would expect any RC osc to be rather worse, as the underlying assumption is of precisely EQUAL time slices. Absolute frequency is not so important, but jitter and stability are.

    I've got two ideas why the PLL makes the conversion worse. First jitter like you suggest Jmg. Second, even at PLL2x the VCO is running at 80MHz with 40MHz, and 20MHz present in the VCO divider. I think the noise from all this extra clocking is screwing up the input pin's transition level. Specifically the input pins are likely sampled right at the start of a clock cycle. The circuit would be particularly quiet at this sampling time without the PLL running.

    Also, Jmg I don't think application code will disturb the ADC (much) as long as the counter PLLs are inactive. My current code now generates audio too. I've used DUTY mode and NCO mode pwm, both in diffrential output mode, and both idling at 50% duty cycle. I haven't seen a large increase in idle noise due to this. Though I have yet to get some more recent data into excel to compare RMS noise. Even with the 8ohm speaker hooked between the pins, I didn't notice a large increase in noise. (love how tough the Prop is!)

    Lawson
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-25 10:26
    jmg wrote: »
    Easy enough to check - however, I would expect any RC osc to be rather worse, as the underlying assumption is of precisely EQUAL time slices. Absolute frequency is not so important, but jitter and stability are.

    EQUAL time slices are not a requirement. Unequal slices have the effect of shifting the operating point. Jitter and stability, yes, especially insofar as it lies within the frequency band of the input signal. If it is much higher it might qualify as dither (if uncorrelated) and actually help the accuracy.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-25 11:00
    jmg wrote: »
    If you want to build a 4 layer test bench that is purely Prop-engined, I can think of a couple of test items to add to a layout.

    a) an option to bias the charge caps, C0,C1 to prop pins, which are then pulled HI and LO.

    These will give local-power-levels, as they will come from the supply rails nearest to the Pin Buffer.
    I've added provision for two additional pin connections to the summing junction. I added them for a different reason, 1) to implement a span calibration such as it is outlined in AN008, and 2) to implement a pair of additional inputs to the summing junction in order to provide DC or perhaps dynamic offset for a small signal riding on DC bias. I've left provision for the capacitors to Vdd and Vss. But I can try your idea. I'm skeptical about it though, that capacitors attached to the pins will properly sample the supply rails. I think I've tried that before with disappointing results. Resistance of the pin driver is in series with the capacitor, which makes the combination a low-pass. The transients we are talking about are due to the nanosecond transitions of the pin drivers resonating with the circuit parasitics.
    b) You can lower the equivalent SDM sample rate, but still have a high clock, by using a divider from Q to inject a few hundred mV of positive feedback to the Charge cap cold ends. ( Negative Feedback is from QN ).
    c) Working on the idea that jitter and noise to some moderate precision are unavoidable, you can add parts that deliberately sweep the operating point over a few tens of mV.
    Not sure what you are saying here.
    d) an option for a 1G Logic buffer, to clean AV+, AV- supply rails. This should be a fast, low skew part if it is not to degrade the balance.
    Yes, this is not quite pure prop, but it does allow a measurement on the supply-contribution to noise floors.
    That remains an intriguing possibility once it is all on a proper 4-layer board. It has to include a high speed comparator such as the 4.5ns LT1719 also tied to a calm power supply, isolated from that of the logic buffer. I'll leave that for another iteration!


    As an aside, this discussion about has been going on now for over 6 years!
    ADC and DAC example
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-25 11:04
    Lawson,
    Are you doing this with the textbook circuit, 100kΩ feedback, 1nF (X7R or COG?) capacitors? Anything connected to the input?
  • jmgjmg Posts: 14,847
    edited 2012-08-25 16:43
    EQUAL time slices are not a requirement. Unequal slices have the effect of shifting the operating point.

    Correct, and that "shift the operating point" is indistinguishable from a variation in input voltage aka noise.
    The counter samples on each clock edge, and implicit in that, is that all bits represent an equal charge weight over duration of the total sample time.
  • jmgjmg Posts: 14,847
    edited 2012-08-25 17:15
    I've added provision for two additional pin connections to the summing junction. I added them for a different reason, 1) to implement a span calibration such as it is outlined in AN008, and 2) to implement a pair of additional inputs to the summing junction in order to provide DC or perhaps dynamic offset for a small signal riding on DC bias. I've left provision for the capacitors to Vdd and Vss. But I can try your idea. I'm skeptical about it though, that capacitors attached to the pins will properly sample the supply rails. I think I've tried that before with disappointing results. Resistance of the pin driver is in series with the capacitor, which makes the combination a low-pass. The transients we are talking about are due to the nanosecond transitions of the pin drivers resonating with the circuit parasitics.

    You can also add a Cap VR+ to VR-. Series R is around 12 ohms. I would expect the biggest gains from a 'digitally active' prop.
    One just running an ADC will have little noise not generated by its own action.
    Not sure what you are saying here.

    Effectively it is the same as the dither you mention above, only intentionally generated as a low level triangle wave.
    Such generation can come for free from the Prop COG, it just costs one more pin.

    That remains an intriguing possibility once it is all on a proper 4-layer board. It has to include a high speed comparator such as the 4.5ns LT1719 also tied to a calm power supply, isolated from that of the logic buffer. I'll leave that for another iteration!

    The 1G Logic buffer (or the equivalent SPCO analog sw) is on the Driver side, so it is very cheap and fully digital.
    Again, this would buy you more on a 'busy' prop, than one doing only ADC.

    One 'reality check' in any external parts, is you need to keep under the cost of an external 24b ADC, and the LT1719 is well over that.

    On the input side, you do not need a comparator, you can use a fast OpAmp as the true integrator instead.

    Spice runs suggest the OpAmp needs to the 'quite good', and it needs to be both fast, and have low offset/bias currents.
    That's not a 10c part, but somewhere around $1 can get 100+MHz, and good slew rates, and spice says is ok for 5-20MHz region clocks.


    The opamp creates a classic mixed sawtooth output, and the cap is chosen to be much lower than a Prop RC, as that gives higher slew rates and now Prop input threshold/noise changes on the D-FF are not summed to the input voltage.

    If we model the D-FF reflected noise as around 12-13 bits, then a 1V integrator swing, will drive that down by another 10-11 bits.
  • LawsonLawson Posts: 870
    edited 2012-08-25 18:28
    jmg wrote: »
    Spice runs suggest the OpAmp needs to the 'quite good', and it needs to be both fast, and have low offset/bias currents.
    That's not a 10c part, but somewhere around $1 can get 100+MHz, and good slew rates, and spice says is ok for 5-20MHz region clocks.

    Do you have any non-unity-gain stable op-amps to suggest? If a capacitor is added between the summing junction of the op-amp and ground/power, high frequency gain can be pushed high enough for stability. Far as I know the main cost is some bandwidth. (and maybe more power supply noise?) This would gain lower input noise, and higher slew rates.

    Also if we're adding parts, I'd personally add a 1G D-flipflop before adding an external buffer. Just as cheap, no extra gate lag, and the input and output would both be able to benefit from a cleaner power supply. (and next part would be an op-amp integrator) Might also be fun to throw a 74AC534 at the problem. 9-pins and $0.85/1ea for 8 ADCs is tempting.

    Lawson.

    P.S. Yes I'm using the component values suggested by the Sigma Delta App Note. 2x 1nF and 120Kohm.
  • jmgjmg Posts: 14,847
    edited 2012-08-25 19:48
    Lawson wrote: »
    Do you have any non-unity-gain stable op-amps to suggest?
    The LTC6246 gives good simulation results clocked ~5-20MHz, and has 180MHz BW and 90V/us slew.
    The OPA354 looks in a similar class.
  • Tracy AllenTracy Allen Posts: 6,577
    edited 2012-08-26 09:55
    jmg, could you draw out the circuit you're talking about and using for the Spice simulations? We might be thinking of quite different arrangements.

    "On the input side, you do not need a comparator, you can use a fast OpAmp as the true integrator instead."

    1) No comparator? The accuracy or at least the stability of the quantizer is of paramount importance. The Propeller threshold is not symmetrical, it drifts with time and temperature, and there is the underlying noise issue. Are you qualifying that by "on the input side"? What is being integrated is usually linear combination of the input signal and the digital feedback.

    2) True integrator? The capacitor*2 in the standard propeller circuit is I think operating pretty close to being a true integrator. To first order the dV/dt ramps at the summing junction are linear, and the summing junction voltage is constant just as you have in an op-amp integrator. Back when we were deep into the math in this thread (page 4), Peter Verkaik did his derivation using exponentials and it gave essentially the same result as the linear approximation.
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