Microchip expand SPI SRAM (finally)
jmg
Posts: 15,183
After a long wait, finally we see more members of SPI SRAM!! - and NVSRAM too
http://www.eetimes.com/electronics-products/electronic-product-reviews/processors/4392260/Microchip-expands-serial-SRAM-lineup
* 512 Kb and 1 Mb SPI
* Speeds of up to 80 Mbps quad-SPI, or SQI, protocol,
* Two additional family members – the 23LCV512 and 23LCV1024 – offer the industry’s most cost-effective options for non-volatile, unlimited-endurance RAM, via battery backup.
They feature fast dual-SPI (SDI) throughput of 40 Mbps and low active and sleep currents.
* Serial NVSRAM devices feature high-speed operation without the high pin counts of parallel NVSRAM, and comparable power consumption to FRAM, all at a fraction of the price. Beneficial for applications such as meters, black boxes and other data recorders, which require unlimited endurance or instantaneous writes along with non-volatile storage.
Pricing starts at $1.16 each in 10,000-unit quantities for the four volatile devices.
The 23A1024 and 23LC1024 are available now for sampling and volume production.
The 23A512 and 23LC512 are expected to be available for sampling and volume production in October.
The two non-volatile devices – the 23LCV512 and 23LCV1024 – start at $1.32 each in 10,000-unit quantities, with sampling and volume production expected in October.
Hmm, I see what Microchip call NVSRAM, is not what everyone else does.
Microchip's is merely a Battery backed RAM, with a Battery Pin...
I expect that little bit of semantic gymnastics will get them into trouble
http://www.eetimes.com/electronics-products/electronic-product-reviews/processors/4392260/Microchip-expands-serial-SRAM-lineup
* 512 Kb and 1 Mb SPI
* Speeds of up to 80 Mbps quad-SPI, or SQI, protocol,
* Two additional family members – the 23LCV512 and 23LCV1024 – offer the industry’s most cost-effective options for non-volatile, unlimited-endurance RAM, via battery backup.
They feature fast dual-SPI (SDI) throughput of 40 Mbps and low active and sleep currents.
* Serial NVSRAM devices feature high-speed operation without the high pin counts of parallel NVSRAM, and comparable power consumption to FRAM, all at a fraction of the price. Beneficial for applications such as meters, black boxes and other data recorders, which require unlimited endurance or instantaneous writes along with non-volatile storage.
Pricing starts at $1.16 each in 10,000-unit quantities for the four volatile devices.
The 23A1024 and 23LC1024 are available now for sampling and volume production.
The 23A512 and 23LC512 are expected to be available for sampling and volume production in October.
The two non-volatile devices – the 23LCV512 and 23LCV1024 – start at $1.32 each in 10,000-unit quantities, with sampling and volume production expected in October.
Hmm, I see what Microchip call NVSRAM, is not what everyone else does.
Microchip's is merely a Battery backed RAM, with a Battery Pin...
I expect that little bit of semantic gymnastics will get them into trouble
Comments
http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2698&redirects=sram
http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en559066
Actually we did to a point. As long as it responds to the SPI read command it can be used for boot. Then the same device can be accessed as a 4 bit part after startup (and 2x 4 bit parts read a byte at a time). I begged Chip personally for this in late October and kept up to date with whether the pin configuration actually would be implemented correctly since. Kye verified it last week.
Yes, such devices were clearly going to arrive sometime....
That's a board issue. The problem before according to the spec was that CLK and DATA were in the wrong order causing data bits to be non-contiguous.
Yes, but that is not quite native hardware - instead you use valuable horsepower just wiggling pins and shuffling nibbles, slowly.
Execute in place is getting common on chips these days, and that uses native hardware to run a QSPI (or even DDR.QSPI) as a code fetch mechanism.
It removes, or softens, a constraint of cheaper FAB process, which is 'less memory than everyone else'..
Do you mean the physical Pin-mapping was not done thinking of QuadSPI at all, but that is now fixed, and so simpler Software support results ?
Essentially it was not explicitly specified. The P8x32a chip legacy had SCL/SDA in the wrong place, and I assumed the worst (the new spec doesn't show any connections other than XI/XO power ground and data pins).
Why not?
Yup. That's why I said "to a point."
So - 1 megabit is 128 kilobytes. That should be enough for some decent sized C programs. Use the cache driver similar to the SD one?
I see it is a "future product". I wonder if we could emulate this in hardware with two 23S17 chips and a 128 to 512k sram chip?
You mean with existing spi sram chips? Are they the 32 kilobyte ones? That is just a little small for my C programs, but 128k would do nicely.
Thinking aloud, if you have lots of 32k chips, you presumably need lots of chip selects. I wonder if one could share clk, di and do for an SD card and lots of SPI ram chips, and have a MCP23008 on the I2C bus to select which SPI device to use?
Drop 23LC1024 into findchips.com
You are partly right here. At least pull-up resistors would need to be added, as the default 1 bit Boot code is likely to float them.
The Boot code could define them as HI, and save the resistors.
On a Prop 2, I think I'd prefer a defined and documented QuadSPI loader pin allocate, as pins are not quite as precious as on a Prop 1, and performance will matter more.
Nice one
This really hits the sweet spot for C programs. 128k for program and 32k in hub for data and it is one little 8 pin chip. So many other external ram solutions either use lots of pins, or lots of chips. This really opens up a lot of possibilities. Time to fire up Eagle and test out some ideas!
You could try SpinSocket Flash with up to 32MB of flash and SpinSocket SRAM with 8 of these chips for 1MB.
Just SpinSocket Flash with one Flash chip and one SRAM chip could work too. I need to finish the drivers though.
As you can see, I've been waiting for these chips
With minor changes. The new parts have 24 bit address, so are more compatible with QSPI Flash parts, and they do have the Quad Mode opcodes, which then expect all transactions in Nibbles.
That is slightly different wrt the Flash, which have a choice of
* 1-bit (8 CLKS) for opcode, thereafter Nibbles for 24 bit address (6 clocks) & data etc
* A sticky opcode mode via M4-5, which can just repeat Adr.Data, all as Nibbles
The Winbond QSPI Flash parts also have 2 bytes turnaround, vs 1 byte on QSPI @ Microchip.
So a common library could be used, with a couple of Flash/SRAM decisions.
Lots of possibilities. In the IDE you could replicate the F10 and F11 of the proptool and F10 sends it to SPI ram during the development stage and then F11 sends it to more permanent storage such as flash or SD card when it is finished.
Thinking about a simple demo board and the pins available. 2 for eeprom, 2 for download, 2 for keyboard, 4 for SD card, 4 for this sram, 8 for shared VGA/TV (add resistors for the one you want) and 2 for audio output. That is 24 pins leaving 8 spare. There are many other combinations, but this is one that would be very cheap to make and would be able to run decent C programs doing clever things that are hard to do in Spin like reloading cogs multiple times with new code on the fly.
Of course Spin could use this board, but by the time you put in the buffer for VGA, the keyboard driver, SD driver and audio driver, there is hardly any code space left for your program. But with C, and this one little sram chip, you can have lots of space for a program. And do things like use more of the hub ram for screen buffer so get better screen resolution. It really opens up a lot of possibilities.
/CS would always be needed as it re-primes the Opcode state engine..
Thanks for posting: those are some seriously interesting chips! BTW, although you've never divulged your location, the title of this thread gives it away. AFAIK, only Brits refer to collective nouns, such as companies, in the plural.
-Phil
Thanks jmg. I think this could be a very simple little board. Back to Eagle...