"AND"
mikea
Posts: 283
I want to test a circuit to make sure pins 5, and 6 are not high at the same time before i use a transistor h bridge. Does this test expression look ok? I didn't expect it to, but pin 7 goes high right away. Is there a good way to prevent the pins from crossing paths other than a mechanical relay, i have a hip 4081 but want to keep it as simple as possible?-thanks-mike
dira[5..7]~~ repeat if outa[6]~~ and outa[5]~~ outa[7]~~
Comments
I'd suggest having an else, at least while troubleshooting, for sanity
like Dr_Acula I do not understand why outa[6]==1 can work at all. Should that not be ina[7]==1? why outa for reading ?
Enjoy!
Mike
Or do you devote two more pins to sampling the actual outputs? But no point in that - by the time the code finds this has happened, and shuts down every cog, the damage may be done.
Or - do you have a hardware solution. That was how I have always built bridge circuits - use a few transistors or logic gates to make sure the error condition never comes up.
Or - do you just code very carefully, in which case no need to check for errors?
BTW it will be important for the bridge to default to off (? pull down resistors) as the propeller pins start off at HiZ (which in practice probably means they are going up and down due to stray RF voltages, mains wiring, flouro lights etc).
ahh. Thank you.
Still ina[1] would make more sense wouldn't it? Just for understanding?
Enjoy!
Mike
as allways a step ahed. yes. I understand. Thank you again.
Enjoy!
Mike
One solution might be to explicitly output every pin on every change. eg change
to
And make sure that an off always happens before an on, so the pin order changes above and below the "else"
and maybe add the code for the condition where both relays are off, whatever that pulsewidth is?
I'm not quite sure if a fuse is preventative protection
Look into proper MOSFET drivers - many of those have analog sense feedback, that delays one FETs ON until the other really is OFF, and some have hardware enable lines to connect to a Power-Good reset type signal, for extra brown out area protection.
With large power fets, and large GATE C's there can be appreciable delays from the uC asking for a change, and the device actually turning off.
You can do this in software too, with a 3rd state that is 'all off' that you apply for a few hundred ns between the active states.
If software always explicitly complements, or both-off's, then in a working system crow-bar effects should be avoided, but on a run-away/corrupted system assuming correct software is optimistic.
That's why some also use hardware.