Wow! It sounds like you've really nailed what needs to be done. Good job! This is going to be something really valuable.
Thanks Chip.
I think I have the rest figured out - just need to reset the unstuff counter if I receive a valid bit.
A question..
Do we have room for the instruction RxUSB D,S/# ?
Alternately, we could use a fixed location such as $1F0. Your thoughts?
RxUSB D, S/# WZ,WC
where
S/# is the PinPair# and Poly bits
S[31..9] = unused
S[8..7] = 00= CRC5 USB
01= CRC16 USB
10= CRC16 CCITT
11= undefined
S[6..0] = D-/D+ Pin Pair #0..127
The pin pair is always a pair of pins mod 2. ie nnnnnnx where x=0 and x=1 for the pair.
If the pin pair is even (S[0]=0) then J is the lowest pin and K is the higher pin of the consecutive pair
If the pin pair is odd (S[0]=1) then K is the lowest pin and J is the higher pin of the consecutive pair.
This arrangement allows for simple LS and FS by making the pin pair even or odd.
D is the cog register storing a 32 bit field...
D[31..16] = crc16
D[15] = K new pin value
D[14] = J new pin value
D[13..11] = unstuff counter 3 bits
D[10..8] = bit counter 3 bits
D[7..0] = data byte accumulation
Z = data byte ready (8 bits)
C = SE0/SE1
Thanks Chip.
I think I have the rest figured out - just need to reset the unstuff counter if I receive a valid bit.
A question..
Do we have room for the instruction RxUSB D,S/# ?
Alternately, we could use a fixed location such as $1F0. Your thoughts?
RxUSB D, S/# WZ,WC
where
S/# is the PinPair# and Poly bits
S[31..9] = unused
S[8..7] = 00= CRC5 USB
01= CRC16 USB
10= CRC16 CCITT
11= undefined
S[6..0] = D-/D+ Pin Pair #0..127
The pin pair is always a pair of pins mod 2. ie nnnnnnx where x=0 and x=1 for the pair.
If the pin pair is even (S[0]=0) then J is the lowest pin and K is the higher pin of the consecutive pair
If the pin pair is odd (S[0]=1) then K is the lowest pin and J is the higher pin of the consecutive pair.
This arrangement allows for simple LS and FS by making the pin pair even or odd.
D is the cog register storing a 32 bit field...
D[31..16] = crc16
D[15] = K new pin value
D[14] = J new pin value
D[13..11] = unstuff counter 3 bits
D[10..8] = bit counter 3 bits
D[7..0] = data byte accumulation
Z = data byte ready (8 bits)
C = SE0/SE1
We'll make room, don't worry. Looks fantastic, like you've identified everything it must do.
Thanks Chip & Bill.
Think I might have all the logic done ready for testing except for syntax problems. I am sure it can be written simpler, but as long as I can convey what needs to be done I'll be happy.
Chip, while I think of it, the GETZC instruction.
A while ago I suggested adding an #0-31 parameter (default 0) which rotates the D value right by 0..31 places before setting ZC=D[1:0]. (D remains unchanged as in NR)
This permits full 4 case decoding simply with the Z & C flags.
It will be particularly useful now we have Z&C being saved in various positions with CALLs etc.
I haven't been keeping up with all the latest developments with the P2 but I remember someone mentioning a general purpose CRC instruction a while back and was wondering if that was still being considered for release? Even a bit-wise crc instruction could come in handy.
A question..
Do we have room for the instruction RxUSB D,S/# ?
Alternately, we could use a fixed location such as $1F0. Your thoughts?
RxUSB D, S/# WZ,WC
where
S/# is the PinPair# and Poly bits
S[31..9] = unused
S[8..7] = 00= CRC5 USB
01= CRC16 USB
10= CRC16 CCITT
11= undefined
S[6..0] = D-/D+ Pin Pair #0..127
The pin pair is always a pair of pins mod 2. ie nnnnnnx where x=0 and x=1 for the pair.
If the pin pair is even (S[0]=0) then J is the lowest pin and K is the higher pin of the consecutive pair
If the pin pair is odd (S[0]=1) then K is the lowest pin and J is the higher pin of the consecutive pair.
This arrangement allows for simple LS and FS by making the pin pair even or odd.
D is the cog register storing a 32 bit field...
D[31..16] = crc16
D[15] = K new pin value
D[14] = J new pin value
D[13..11] = unstuff counter 3 bits
D[10..8] = bit counter 3 bits
D[7..0] = data byte accumulation
Z = data byte ready (8 bits)
C = SE0/SE1
See also the USB thead.
Once you have encapsulated RxUSB verilog, it is a small step to pace that on a Timer, and it becomes WAITUSB, which is now read once per byte (or it exits earlier on Flags)
This also then allows the timer to have a edge-snap mode, to resync on the USB edges.
Counter needs a reload (baud) mode, with an optional phased edge reset.
Chip,
Do the background instructions that take multiple clocks (such as the cordic, big multipier, etc) consume large amounts of silicon (apart from the actual processing logic)?
What I am getting at, does it use a lot of silicon to set say the USB receiver off running in the background, and permit the cog to continue on with other processing while a byte (or more) is grabbed?
I have been resisting this path because it lacks general purpose use, but wondered if it is worth pursuing.
Chip,
Do the background instructions that take multiple clocks (such as the cordic, big multipier, etc) consume large amounts of silicon (apart from the actual processing logic)?
What I am getting at, does it use a lot of silicon to set say the USB receiver off running in the background, and permit the cog to continue on with other processing while a byte (or more) is grabbed?
I have been resisting this path because it lacks general purpose use, but wondered if it is worth pursuing.
A USB state machine running in the background, reading and writing AUX would not be very big, at all. I don't think there's anything about USB that lends itself to general-purpose reuse, so it might as well be USB-only. If we could build a complete USB state machine, it might be an ideal approach.
A USB state machine running in the background, reading and writing AUX would not be very big, at all. I don't think there's anything about USB that lends itself to general-purpose reuse, so it might as well be USB-only. If we could build a complete USB state machine, it might be an ideal approach.
Chip,
Do the Counter have a reload mode, ideally with a external edge reset ?
A simple mode like that, would allow a Counter to be set to clock the USB state engine, and probably 1 level of Data storage is needed to give more time tolerance.
I think this could be emulated in SW @ 1.5MHz to prove the details.
Chip,
Do the Counter have a reload mode, ideally with a external edge reset ?
A simple mode like that, would allow a Counter to be set to clock the USB state engine, and probably 1 level of Data storage is needed to give more time tolerance.
I think this could be emulated in SW @ 1.5MHz to prove the details.
The counters can count the frequency of edges and the durations of states, but they don't have a reload mode like you are asking about.
A special circuit can be made for the USB handler, though. In many instances, it's not the guts of a circuit that take lots of space, but all the conduit to make it breathe. If we encapsulated it, it might be the best way to go.
The counters can count the frequency of edges and the durations of states, but they don't have a reload mode like you are asking about.
A special circuit can be made for the USB handler, though. In many instances, it's not the guts of a circuit that take lots of space, but all the conduit to make it breathe. If we encapsulated it, it might be the best way to go.
Good point, it's not a very large timer, lowest would be /4 for 48MHz to 12MHz and highest to cover 1.5MHz from 200MHz core, is /133.33 so an 8 bit reload/Rst counter / 'baud divider' is all that is needed to cover practical clock ranges, with a 50% compare for the sample point for both even and odd numbers.
Can anyone think of a better name than TCHECK? There should be some single word that could make up most of the name. I used "check" like one would check a basketball with an opposition teammate before starting play again. The word "register" applies, too, but it's too long and means, well... registers.
Chip,
As soon as you have the instruction summary (the section at the end of the docs) would you like to post it so I can put it into the spreadsheet and repost.
Thanks.
Chip,
As soon as you have the instruction summary (the section at the end of the docs) would you like to post it so I can put it into the spreadsheet and repost.
Thanks.
I just noticed that you got rid of the wr bit. Since there are still some unary/nullary instruction slots left, can you add an instruction that makes the next instruction's dest not get written? It would be just as fast and use one long less cogram than copying the dest to a temporary register and doing your operation on the temporary register:
old way:
mov t1, x
<whatever> t1, y wz, wc
t1 res 0
new way:
nr ' new instruction
<whatever> x, y wz, wc
Thanks,
electrodude
EDIT: nr would only work inside a tlock or in a single-tasked program, making the mov method easier for multitasking. My nr instruction is still easier for singletasking.
I just noticed that you got rid of the wr bit. Since there are still some unary/nullary instruction slots left, can you add an instruction that makes the next instruction's dest not get written? It would be just as fast and use one long less cogram than copying the dest to a temporary register and doing your operation on the temporary register:
old way:
mov t1, x
<whatever> t1, y wz, wc
t1 res 0
new way:
nr ' new instruction
<whatever> x, y wz, wc
Thanks,
electrodude
EDIT: nr would only work inside a tlock or in a single-tasked program, making the mov method easier for multitasking. My nr instruction is still easier for singletasking.
Nice idea!
AUGNR 'next instruction does not write out the result, only affects Z & C flags according to WZ & WC
I just noticed that you got rid of the wr bit. Since there are still some unary/nullary instruction slots left, can you add an instruction that makes the next instruction's dest not get written? It would be just as fast and use one long less cogram than copying the dest to a temporary register and doing your operation on the temporary register:
old way:
mov t1, x
<whatever> t1, y wz, wc
t1 res 0
new way:
nr ' new instruction
<whatever> x, y wz, wc
Thanks,
electrodude
EDIT: nr would only work inside a tlock or in a single-tasked program, making the mov method easier for multitasking. My nr instruction is still easier for singletasking.
This could work, per task, but could you give me an instruction sequence that would benefit from this feature? I was just looking at the instruction set and I don't see any obvious cases where blocking the result writing would gain anything. If you can convince me, I'll do it. And better yet, we could have an instruction that actually redirects the result writing to another register 'NEXTWR D/#'.
That NEXTWR seems useful as it gives you the ability to do any instruction of the form "D2 = D1 OP S" and D1 is not destroyed in the process. Could be very useful if D1 is needed multiple times after its initial use and you don't want to make multiple copies of it along the way. However you still need to put in the extra NEXTWR instruction each time you need this. It would need to be stored per task state too. If $1F1 is not used in the code, you could put the dummy result there each time using NEXTWR #$1f1.
SHR/SHL/ROR/ROL/RLC/RCR/AND/XOR <reg>,<#nnn NR WZ,WC 'check bit(s)
We can now check a bit using TESTB but it would mostly use a reg. There are cases where the NR was quite useful. There are of course ways around this, using a temp register.
IMHO a single AUGNR would be most useful. To work just like AUGS and AUGD does. This way, all the standard instructions such as the above, plus things like NEG, ADD, SUB, etc could be made to work using the AUGNR preceding the instruction. Would this be difficult?
Another instruction I mentioned a little earlier was to put D[1:0 + offset] into Z & C using wz and wc. By rotating D to the right #offset times, we could use any bit pair to set Z & C flags. This permits full 4 way decoding quickly. I thought that SETZC could be extended to be SETZC D/#,#0..31 using say
ZCL- 1111111 ZC L CCCC DDDDDDDDD 1111nnnnn SETZC D/#,#nnnnn 'where nnnnn shifts D right 0..31 places (default is 30). Note D is not written.
Postedit:
NEXTWR D/#
Could be extremely useful for giving a separate result from 2 inputs (D & S). Maybe we could utilise the special register $1F1 to mean NR.
IMHO this would be more versatile than AUGNR. Maybe AUGDEST might be a better name (since it is like AUGS and AUGD).
Chip
Does SETMASK, WIDEBM, WIDEWM and WIDELM still exist? See here
Only these:
WRWIDE S/PTRA/PTRB
WRWIDEM D/#,S/PTRA/PTRB
WRWIDEM lets you specify a 32-mask in D/# where 1's inhibit individual byte writes within the 32-byte WIDE. So, by making it atomic, we don't need SETMASK.
Comments
I think I have the rest figured out - just need to reset the unstuff counter if I receive a valid bit.
A question..
Do we have room for the instruction RxUSB D,S/# ?
Alternately, we could use a fixed location such as $1F0. Your thoughts?
RxUSB D, S/# WZ,WC where S/# is the PinPair# and Poly bits S[31..9] = unused S[8..7] = 00= CRC5 USB 01= CRC16 USB 10= CRC16 CCITT 11= undefined S[6..0] = D-/D+ Pin Pair #0..127 The pin pair is always a pair of pins mod 2. ie nnnnnnx where x=0 and x=1 for the pair. If the pin pair is even (S[0]=0) then J is the lowest pin and K is the higher pin of the consecutive pair If the pin pair is odd (S[0]=1) then K is the lowest pin and J is the higher pin of the consecutive pair. This arrangement allows for simple LS and FS by making the pin pair even or odd. D is the cog register storing a 32 bit field... D[31..16] = crc16 D[15] = K new pin value D[14] = J new pin value D[13..11] = unstuff counter 3 bits D[10..8] = bit counter 3 bits D[7..0] = data byte accumulation Z = data byte ready (8 bits) C = SE0/SE1Your USB instruction looks REALLY good.
We'll make room, don't worry. Looks fantastic, like you've identified everything it must do.
Think I might have all the logic done ready for testing except for syntax problems. I am sure it can be written simpler, but as long as I can convey what needs to be done I'll be happy.
Chip, while I think of it, the GETZC instruction.
A while ago I suggested adding an #0-31 parameter (default 0) which rotates the D value right by 0..31 places before setting ZC=D[1:0]. (D remains unchanged as in NR)
This permits full 4 case decoding simply with the Z & C flags.
It will be particularly useful now we have Z&C being saved in various positions with CALLs etc.
Going to get some sleep now
I haven't been keeping up with all the latest developments with the P2 but I remember someone mentioning a general purpose CRC instruction a while back and was wondering if that was still being considered for release? Even a bit-wise crc instruction could come in handy.
Cheers,
David
See also the USB thead.
Once you have encapsulated RxUSB verilog, it is a small step to pace that on a Timer, and it becomes
WAITUSB, which is now read once per byte (or it exits earlier on Flags)
This also then allows the timer to have a edge-snap mode, to resync on the USB edges.
Counter needs a reload (baud) mode, with an optional phased edge reset.
Do the background instructions that take multiple clocks (such as the cordic, big multipier, etc) consume large amounts of silicon (apart from the actual processing logic)?
What I am getting at, does it use a lot of silicon to set say the USB receiver off running in the background, and permit the cog to continue on with other processing while a byte (or more) is grabbed?
I have been resisting this path because it lacks general purpose use, but wondered if it is worth pursuing.
Yes, quite an impressive number
A USB state machine running in the background, reading and writing AUX would not be very big, at all. I don't think there's anything about USB that lends itself to general-purpose reuse, so it might as well be USB-only. If we could build a complete USB state machine, it might be an ideal approach.
Chip,
Do the Counter have a reload mode, ideally with a external edge reset ?
A simple mode like that, would allow a Counter to be set to clock the USB state engine, and probably 1 level of Data storage is needed to give more time tolerance.
I think this could be emulated in SW @ 1.5MHz to prove the details.
The counters can count the frequency of edges and the durations of states, but they don't have a reload mode like you are asking about.
A special circuit can be made for the USB handler, though. In many instances, it's not the guts of a circuit that take lots of space, but all the conduit to make it breathe. If we encapsulated it, it might be the best way to go.
Good point, it's not a very large timer, lowest would be /4 for 48MHz to 12MHz and highest to cover 1.5MHz from 200MHz core, is /133.33 so an 8 bit reload/Rst counter / 'baud divider' is all that is needed to cover practical clock ranges, with a 50% compare for the sample point for both even and odd numbers.
Don't get too excited because probably at lease .4 Million views was just me trying to figure out what you guys were talking about. LOL
WAITREG? Or WAITRNZ?
Computer Engineering, VLSI Lab, USB2.0 Protocol Engine Project
Figure 6 – Configured Final State Machine
http://engineering.biu.ac.il/files/engineering/shared/PE_project_book_0.pdf
As soon as you have the instruction summary (the section at the end of the docs) would you like to post it so I can put it into the spreadsheet and repost.
Thanks.
Here it is:
Prop2_Instructions_2014_03_12.txt
ZCDS (for D column: W=write, M=modify, R=read, L=read/immediate) ---------------------------------------------------------------------------------------------------------------------------------------------- ZCWS 0000000 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRA/PTRB (waits for hub) ZCWS 0000001 ZC I CCCC DDDDDDDDD SSSSSSSSS RDBYTEC D,S/PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000010 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRA/PTRB (waits for hub) ZCWS 0000011 ZC I CCCC DDDDDDDDD SSSSSSSSS RDWORDC D,S/PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000100 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRA/PTRB (waits for hub) ZCWS 0000101 ZC I CCCC DDDDDDDDD SSSSSSSSS RDLONGC D,S/PTRA/PTRB (waits for hub if dcache miss) ZCWS 0000110 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUX D,S/#0..$FF/PTRX/PTRY ZCWS 0000111 ZC I CCCC DDDDDDDDD SSSSSSSSS RDAUXR D,S/#0..$FF/PTRX/PTRY ZCMS 0001000 ZC I CCCC DDDDDDDDD SSSSSSSSS ISOB D,S/# ZCMS 0001001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOTB D,S/# ZCMS 0001010 ZC I CCCC DDDDDDDDD SSSSSSSSS CLRB D,S/# ZCMS 0001011 ZC I CCCC DDDDDDDDD SSSSSSSSS SETB D,S/# ZCMS 0001100 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBC D,S/# ZCMS 0001101 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S/# ZCMS 0001110 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S/# ZCMS 0001111 ZC I CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S/# ZCMS 0010000 ZC I CCCC DDDDDDDDD SSSSSSSSS ANDN D,S/# ZCMS 0010001 ZC I CCCC DDDDDDDDD SSSSSSSSS AND D,S/# ZCMS 0010010 ZC I CCCC DDDDDDDDD SSSSSSSSS OR D,S/# ZCMS 0010011 ZC I CCCC DDDDDDDDD SSSSSSSSS XOR D,S/# ZCMS 0010100 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXC D,S/# ZCMS 0010101 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S/# ZCMS 0010110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S/# ZCMS 0010111 ZC I CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S/# ZCMS 0011000 ZC I CCCC DDDDDDDDD SSSSSSSSS ROR D,S/# ZCMS 0011001 ZC I CCCC DDDDDDDDD SSSSSSSSS ROL D,S/# ZCMS 0011010 ZC I CCCC DDDDDDDDD SSSSSSSSS SHR D,S/# ZCMS 0011011 ZC I CCCC DDDDDDDDD SSSSSSSSS SHL D,S/# ZCMS 0011100 ZC I CCCC DDDDDDDDD SSSSSSSSS RCR D,S/# ZCMS 0011101 ZC I CCCC DDDDDDDDD SSSSSSSSS RCL D,S/# ZCMS 0011110 ZC I CCCC DDDDDDDDD SSSSSSSSS SAR D,S/# ZCMS 0011111 ZC I CCCC DDDDDDDDD SSSSSSSSS REV D,S/# ZCWS 0100000 ZC I CCCC DDDDDDDDD SSSSSSSSS MOV D,S/# ZCWS 0100001 ZC I CCCC DDDDDDDDD SSSSSSSSS NOT D,S/# ZCWS 0100010 ZC I CCCC DDDDDDDDD SSSSSSSSS ABS D,S/# ZCWS 0100011 ZC I CCCC DDDDDDDDD SSSSSSSSS NEG D,S/# ZCWS 0100100 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGC D,S/# ZCWS 0100101 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S/# ZCWS 0100110 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S/# ZCWS 0100111 ZC I CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S/# ZCMS 0101000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADD D,S/# ZCMS 0101001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUB D,S/# ZCMS 0101010 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDX D,S/# ZCMS 0101011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBX D,S/# ZCMS 0101100 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDS D,S/# ZCMS 0101101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBS D,S/# ZCMS 0101110 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S/# ZCMS 0101111 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S/# ZCMS 0110000 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMC D,S/# ZCMS 0110001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S/# ZCMS 0110010 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S/# ZCMS 0110011 ZC I CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S/# ZCMS 0110100 ZC I CCCC DDDDDDDDD SSSSSSSSS MIN D,S/# ZCMS 0110101 ZC I CCCC DDDDDDDDD SSSSSSSSS MAX D,S/# ZCMS 0110110 ZC I CCCC DDDDDDDDD SSSSSSSSS MINS D,S/# ZCMS 0110111 ZC I CCCC DDDDDDDDD SSSSSSSSS MAXS D,S/# ZCMS 0111000 ZC I CCCC DDDDDDDDD SSSSSSSSS ADDABS D,S/# ZCMS 0111001 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBABS D,S/# ZCMS 0111010 ZC I CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S/# ZCMS 0111011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S/# ZCMS 0111100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S/# ZCMS 0111101 ZC I CCCC DDDDDDDDD SSSSSSSSS SUBR D,S/# ZCMS 0111110 ZC I CCCC DDDDDDDDD SSSSSSSSS MUL D,S/# (waits one clock) ZCMS 0111111 ZC I CCCC DDDDDDDDD SSSSSSSSS SCL D,S/# (waits one clock) ZCWS 1000000 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD2 D,S/# ZCWS 1000001 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD3 D,S/# ZCWS 1000010 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD4 D,S/# ZCWS 1000011 ZC I CCCC DDDDDDDDD SSSSSSSSS DECOD5 D,S/# Z-WS 1000100 Z0 I CCCC DDDDDDDDD SSSSSSSSS ENCOD D,S/# Z-WS 1000100 Z1 I CCCC DDDDDDDDD SSSSSSSSS BLMASK D,S/# Z-WS 1000101 Z0 I CCCC DDDDDDDDD SSSSSSSSS ONECNT D,S/# (waits one clock) Z-WS 1000101 Z1 I CCCC DDDDDDDDD SSSSSSSSS ZERCNT D,S/# (waits one clock) -CWS 1000110 0C I CCCC DDDDDDDDD SSSSSSSSS INCPAT D,S/# -CWS 1000110 1C I CCCC DDDDDDDDD SSSSSSSSS DECPAT D,S/# --WS 1000111 00 I CCCC DDDDDDDDD SSSSSSSSS SPLITB D,S/# (also MERGEN) --WS 1000111 01 I CCCC DDDDDDDDD SSSSSSSSS MERGEB D,S/# (also SPLITN) --WS 1000111 10 I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S/# --WS 1000111 11 I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S/# --MS 10010nn n0 I CCCC DDDDDDDDD SSSSSSSSS GETNIB D,S/#,#0..7 --MS 10010nn n1 I CCCC DDDDDDDDD SSSSSSSSS SETNIB D,S/#,#0..7 --MS 1001100 n0 I CCCC DDDDDDDDD SSSSSSSSS GETWORD D,S/#,#0..1 --MS 1001100 n1 I CCCC DDDDDDDDD SSSSSSSSS SETWORD D,S/#,#0..1 --MS 1001101 00 I CCCC DDDDDDDDD SSSSSSSSS SETWRDS D,S/# --MS 1001101 01 I CCCC DDDDDDDDD SSSSSSSSS ROLNIB D,S/# --MS 1001101 10 I CCCC DDDDDDDDD SSSSSSSSS ROLBYTE D,S/# --MS 1001101 11 I CCCC DDDDDDDDD SSSSSSSSS ROLWORD D,S/# --MS 1001110 00 I CCCC DDDDDDDDD SSSSSSSSS SETS D,S/# --MS 1001110 01 I CCCC DDDDDDDDD SSSSSSSSS SETD D,S/# --MS 1001110 10 I CCCC DDDDDDDDD SSSSSSSSS SETCOND D,S/# --MS 1001110 11 I CCCC DDDDDDDDD SSSSSSSSS SETINST D,S/# --WS 1001111 00 I CCCC DDDDDDDDD SSSSSSSSS <empty> D,S/# --WS 1001111 01 I CCCC DDDDDDDDD SSSSSSSSS THALT D,S/# -CMS 1001111 1C I CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# (waits for CNT, +CNTX if WC) --MS 101000n n0 I CCCC DDDDDDDDD SSSSSSSSS GETBYTE D,S/#,#0..3 --MS 101000n n1 I CCCC DDDDDDDDD SSSSSSSSS SETBYTE D,S/#,#0..3 --WS 1010010 00 I CCCC DDDDDDDDD SSSSSSSSS SETBYTS D,S/# --MS 1010010 01 I CCCC DDDDDDDDD SSSSSSSSS MOVBYTS D,S/# (move bytes in D, S = %11_10_01_00 = D same) --MS 1010010 10 I CCCC DDDDDDDDD SSSSSSSSS PACKRGB D,S/# (S 8:8:8 -> D 5:5:5 << 16 | D >> 16) --WS 1010010 11 I CCCC DDDDDDDDD SSSSSSSSS UNPKRGB D,S/# (S 5:5:5 -> D 8:8:8) --MS 1010011 00 I CCCC DDDDDDDDD SSSSSSSSS ADDPIX D,S/# (waits one clock) --MS 1010011 01 I CCCC DDDDDDDDD SSSSSSSSS MULPIX D,S/# (waits one clock) --MS 1010011 10 I CCCC DDDDDDDDD SSSSSSSSS BLNPIX D,S/# (waits one clock) --MS 1010011 11 I CCCC DDDDDDDDD SSSSSSSSS MIXPIX D,S/# (waits one clock) ZCMS 1010100 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPSW D,S/@ ZCMS 1010101 ZC I CCCC DDDDDDDDD SSSSSSSSS JMPSWD D,S/@ --MS 1010110 00 I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S/@ --MS 1010110 01 I CCCC DDDDDDDDD SSSSSSSSS DJZD D,S/@ --MS 1010110 10 I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S/@ --MS 1010110 11 I CCCC DDDDDDDDD SSSSSSSSS DJNZD D,S/@ --RS 1010111 00 I CCCC DDDDDDDDD SSSSSSSSS JZ D,S/@ --RS 1010111 01 I CCCC DDDDDDDDD SSSSSSSSS JZD D,S/@ --RS 1010111 10 I CCCC DDDDDDDDD SSSSSSSSS JNZ D,S/@ --RS 1010111 11 I CCCC DDDDDDDDD SSSSSSSSS JNZD D,S/@ ZCRS 1011000 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTB D,S/# ZCRS 1011001 ZC I CCCC DDDDDDDDD SSSSSSSSS TESTN D,S/# ZCRS 1011010 ZC I CCCC DDDDDDDDD SSSSSSSSS TEST D,S/# ZCRS 1011011 ZC I CCCC DDDDDDDDD SSSSSSSSS CMP D,S/# ZCRS 1011100 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPX D,S/# ZCRS 1011101 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPS D,S/# ZCRS 1011110 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S/# ZCRS 1011111 ZC I CCCC DDDDDDDDD SSSSSSSSS CMPR D,S/# -CRS 110000n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPEQ D,S/#,#0..3 (waits for pins, plus CNT if WC) -CRS 110001n nC I CCCC DDDDDDDDD SSSSSSSSS WAITPNE D,S/#,#0..3 (waits for pins, plus CNT if WC) ---S 110010n nn I CCCC nnnnnnnnn SSSSSSSSS WAITVID #0..$DFF,S/# (waits for vid if single-task, loops if multi-task) --RS 1100101 11 I CCCC DDDDDDDDD SSSSSSSSS WAITVID D,S/# (waits for vid if single-task, loops if multi-task) --LS 1100110 0L I CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,S/PTRA/PTRB (waits for hub) --LS 1100110 1L I CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,S/PTRA/PTRB (waits for hub) --LS 1100111 0L I CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,S/PTRA/PTRB (waits for hub) --LS 1100111 1L I CCCC DDDDDDDDD SSSSSSSSS WRWIDE D/#,S/PTRA/PTRB (waits for hub) (actually WRWIDEM, also WRWIDE S/PTRA/PTRB) --LS 1101000 0L I CCCC DDDDDDDDD SSSSSSSSS WRAUX D/#,S/#0..$FF/PTRX/PTRY --LS 1101000 1L I CCCC DDDDDDDDD SSSSSSSSS WRAUXR D/#,S/#0..$FF/PTRX/PTRY --LS 1101001 0L I CCCC DDDDDDDDD SSSSSSSSS SETACCA D/#,S/# --LS 1101001 1L I CCCC DDDDDDDDD SSSSSSSSS SETACCB D/#,S/# --LS 1101010 0L I CCCC DDDDDDDDD SSSSSSSSS MACA D/#,S/# --LS 1101010 1L I CCCC DDDDDDDDD SSSSSSSSS MACB D/#,S/# --LS 1101011 0L I CCCC DDDDDDDDD SSSSSSSSS MUL32 D/#,S/# --LS 1101011 1L I CCCC DDDDDDDDD SSSSSSSSS MUL32U D/#,S/# --LS 1101100 0L I CCCC DDDDDDDDD SSSSSSSSS DIV32 D/#,S/# --LS 1101100 1L I CCCC DDDDDDDDD SSSSSSSSS DIV32U D/#,S/# --LS 1101101 0L I CCCC DDDDDDDDD SSSSSSSSS DIV64 D/#,S/# --LS 1101101 1L I CCCC DDDDDDDDD SSSSSSSSS DIV64U D/#,S/# --LS 1101110 0L I CCCC DDDDDDDDD SSSSSSSSS SQRT64 D/#,S/# --LS 1101110 1L I CCCC DDDDDDDDD SSSSSSSSS QSINCOS D/#,S/# --LS 1101111 0L I CCCC DDDDDDDDD SSSSSSSSS QARCTAN D/#,S/# --LS 1101111 1L I CCCC DDDDDDDDD SSSSSSSSS QROTATE D/#,S/# --LS 111000n nL I CCCC DDDDDDDDD SSSSSSSSS CFGPINS D/#,S/#,#0..2 (waits for alt) --LS 1110001 1L I CCCC DDDDDDDDD SSSSSSSSS SETMAP D/#,S/# --LS 1110010 0L I CCCC DDDDDDDDD SSSSSSSSS SETSERA D/#,S/# (config,baud) --LS 1110010 1L I CCCC DDDDDDDDD SSSSSSSSS SETSERB D/#,S/# (config,baud) --LS 1110011 0L I CCCC DDDDDDDDD SSSSSSSSS SETCTRS D/#,S/# (ctrb,ctra) --LS 1110011 1L I CCCC DDDDDDDDD SSSSSSSSS SETWAVS D/#,S/# (ctrb,ctra) --LS 1110100 0L I CCCC DDDDDDDDD SSSSSSSSS SETFRQS D/#,S/# (ctrb,ctra) --LS 1110100 1L I CCCC DDDDDDDDD SSSSSSSSS SETPHSS D/#,S/# (ctrb,ctra) --LS 1110101 0L I CCCC DDDDDDDDD SSSSSSSSS ADDPHSS D/#,S/# (ctrb,ctra) --LS 1110101 1L I CCCC DDDDDDDDD SSSSSSSSS SUBPHSS D/#,S/# (ctrb,ctra) --LS 1110110 0L I CCCC DDDDDDDDD SSSSSSSSS SETXFR D/#,S/# --LS 1110110 1L I CCCC DDDDDDDDD SSSSSSSSS SETMIX D/#,S/# --LS 1110111 0L I CCCC DDDDDDDDD SSSSSSSSS COGRUN D/#,S/# (waits for hub) --LS 1110111 1L I CCCC DDDDDDDDD SSSSSSSSS COGRUNX D/#,S/# (waits for hub) --LS 1111000 0L I CCCC DDDDDDDDD SSSSSSSSS FRAC D/#,S/# --LS 1111000 1L I CCCC DDDDDDDDD SSSSSSSSS <empty> D/#,S/# --LS 1111001 0L I CCCC DDDDDDDDD SSSSSSSSS <empty> D/#,S/# --LS 1111001 1L I CCCC DDDDDDDDD SSSSSSSSS <empty> D/#,S/# --LS 1111010 0L I CCCC DDDDDDDDD SSSSSSSSS JP D/#,S/@ (waits one clock) --LS 1111010 1L I CCCC DDDDDDDDD SSSSSSSSS JPD D/#,S/@ (waits one clock) --LS 1111011 0L I CCCC DDDDDDDDD SSSSSSSSS JNP D/#,S/@ (waits one clock) --LS 1111011 1L I CCCC DDDDDDDDD SSSSSSSSS JNPD D/#,S/@ (waits one clock) --WS 1111100 00 I CCCC DDDDDDDDD SSSSSSSSS LOCBASE D,S/@ (if S: S<<2, if @S: (P+@S)<<2) --MS 1111100 01 I CCCC DDDDDDDDD SSSSSSSSS LOCBYTE D,S/@ (if S: D<<0 + S<<2, if @S: D<<0 + (P+@S)<<2) --MS 1111100 10 I CCCC DDDDDDDDD SSSSSSSSS LOCWORD D,S/@ (if S: D<<1 + S<<2, if @S: D<<1 + (P+@S)<<2) --MS 1111100 11 I CCCC DDDDDDDDD SSSSSSSSS LOCLONG D,S/@ (if S: D<<2 + S<<2, if @S: D<<2 + (P+@S)<<2) --W- 1111101 00 0 CCCC DDDDDDDDD sssssssss LOCINST D,@s (P+s) --R- 1111101 00 1 CCCC DDDDDDDDD sssssssss JMPLIST D,@s (jump to P+s+D) ---- 1111101 01 0 BBAA ddddddddd sssssssss FIXINDA #d,#s / FIXINDB #d,#s / FIXINDS #d,#s / SETINDA #s / SETINDB #d / SETINDS #d,#s ---- 1111101 01 1 nnnn nnnnnnnnn nnniiiiii REPS #1..$10000,#1..64 ---- 1111101 10 n nnnn nnnnnnnnn nnnnnnnnn AUGS #23bits (appends n to upper bits of next immediate S) ---- 1111101 11 n nnnn nnnnnnnnn nnnnnnnnn AUGD #23bits (appends n to upper bits of next immediate D) ---- 1111110 00 0 CCCC 00 nnnnnnnnnnnnnnnn LOCPTRA #abs ---- 1111110 00 0 CCCC 01 nnnnnnnnnnnnnnnn LOCPTRA @rel ---- 1111110 00 0 CCCC 10 nnnnnnnnnnnnnnnn LOCPTRB #abs ---- 1111110 00 0 CCCC 11 nnnnnnnnnnnnnnnn LOCPTRB @rel ---- 1111110 00 1 CCCC 00 nnnnnnnnnnnnnnnn JMP #abs ---- 1111110 00 1 CCCC 01 nnnnnnnnnnnnnnnn JMP @rel ---- 1111110 00 1 CCCC 10 nnnnnnnnnnnnnnnn JMPD #abs ---- 1111110 00 1 CCCC 11 nnnnnnnnnnnnnnnn JMPD @rel ---- wr0 1111110 01 0 CCCC 00 nnnnnnnnnnnnnnnn LINK #abs (jump, write {%00000000000000,Z,C,P} to $000) ---- wr0 1111110 01 0 CCCC 01 nnnnnnnnnnnnnnnn LINK @rel ---- wr0 1111110 01 0 CCCC 10 nnnnnnnnnnnnnnnn LINKD #abs ---- wr0 1111110 01 0 CCCC 11 nnnnnnnnnnnnnnnn LINKD @rel ---- 1111110 01 1 CCCC 00 nnnnnnnnnnnnnnnn CALL #abs ---- 1111110 01 1 CCCC 01 nnnnnnnnnnnnnnnn CALL @rel ---- 1111110 01 1 CCCC 10 nnnnnnnnnnnnnnnn CALLD #abs ---- 1111110 01 1 CCCC 11 nnnnnnnnnnnnnnnn CALLD @rel ---- 1111110 10 0 CCCC 00 nnnnnnnnnnnnnnnn CALLA #abs ---- 1111110 10 0 CCCC 01 nnnnnnnnnnnnnnnn CALLA @rel ---- 1111110 10 0 CCCC 10 nnnnnnnnnnnnnnnn CALLAD #abs ---- 1111110 10 0 CCCC 11 nnnnnnnnnnnnnnnn CALLAD @rel ---- 1111110 10 1 CCCC 00 nnnnnnnnnnnnnnnn CALLB #abs ---- 1111110 10 1 CCCC 01 nnnnnnnnnnnnnnnn CALLB @rel ---- 1111110 10 1 CCCC 10 nnnnnnnnnnnnnnnn CALLBD #abs ---- 1111110 10 1 CCCC 11 nnnnnnnnnnnnnnnn CALLBD @rel ---- 1111110 11 0 CCCC 00 nnnnnnnnnnnnnnnn CALLX #abs ---- 1111110 11 0 CCCC 01 nnnnnnnnnnnnnnnn CALLX @rel ---- 1111110 11 0 CCCC 10 nnnnnnnnnnnnnnnn CALLXD #abs ---- 1111110 11 0 CCCC 11 nnnnnnnnnnnnnnnn CALLXD @rel ---- 1111110 11 1 CCCC 00 nnnnnnnnnnnnnnnn CALLY #abs ---- 1111110 11 1 CCCC 01 nnnnnnnnnnnnnnnn CALLY @rel ---- 1111110 11 1 CCCC 10 nnnnnnnnnnnnnnnn CALLYD #abs ---- 1111110 11 1 CCCC 11 nnnnnnnnnnnnnnnn CALLYD @rel ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000000 COGID D (waits for hub) (doesn't write D if WC) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000001 TASKID D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000010 LOCKNEW D (waits for hub) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000011 GETLFSR D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000100 GETCNT D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000101 GETCNTX D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000110 GETACAL D (waits for mac) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000000111 GETACAH D (waits for mac) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001000 GETACBL D (waits for mac) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001001 GETACBH D (waits for mac) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001010 GETPTRA D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001011 GETPTRB D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001100 GETPTRX D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001101 GETPTRY D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001110 SERINA D (waits for rx if single-task, loops if multi-task, releases if WC) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000001111 SERINB D (waits for rx if single-task, loops if multi-task, releases if WC) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010000 GETMULL D (waits for mul if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010001 GETMULH D (waits for mul if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010010 GETDIVQ D (waits for div if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010011 GETDIVR D (waits for div if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010100 GETSQRT D (waits for sqrt if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010101 GETQX D (waits for cordic if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010110 GETQY D (waits for cordic if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000010111 GETQZ D (waits for cordic if single-task, loops if multi-task) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011000 GETPHSA D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011001 GETPHZA D (clears phsa) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011010 GETCOSA D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011011 GETSINA D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011100 GETPHSB D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011101 GETPHZB D (clears phsb) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011110 GETCOSB D ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000011111 GETSINB D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100000 PUSHZC D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100001 POPZC D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100010 SUBCNT D (subtracts D from CNT, then CNTX if same thread) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100011 GETPIX D (takes 3 clocks, needs 3 clocks in prior two stages, condition only gates writes) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100100 BINBCD D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100101 BCDBIN D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100110 BINGRY D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000100111 GRYBIN D (waits one clock) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101000 ESWAP4 D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101001 ESWAP8 D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101010 SEUSSF D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101011 SEUSSR D ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101100 INCD D (D += $200) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101101 DECD D (D -= $200) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101110 INCDS D (D += $201) ZCM- 1111111 ZC 0 CCCC DDDDDDDDD 000101111 DECDS D (D -= $201) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000110000 POPT0 D (pops from task 0's 4-level stack) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000110001 POPT1 D (pops from task 1's 4-level stack) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000110010 POPT2 D (pops from task 2's 4-level stack) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000110011 POPT3 D (pops from task 3's 4-level stack) ZCW- 1111111 ZC 0 CCCC DDDDDDDDD 000110100 POP D (pops from task's 4-level stack) --L- 1111111 00 L CCCC DDDDDDDDD 001iiiiii REPD D/#1..512,#1..64 (REPD $1FF,#1..64 = infinite repeat, can use REPD #i) --L- 1111111 00 L CCCC DDDDDDDDD 010000000 CLKSET D/# (waits for hub) --L- 1111111 00 L CCCC DDDDDDDDD 010000001 COGSTOP D/# (waits for hub) -CL- 1111111 0C L CCCC DDDDDDDDD 010000010 LOCKSET D/# (waits for hub) -CL- 1111111 0C L CCCC DDDDDDDDD 010000011 LOCKCLR D/# (waits for hub) --L- 1111111 00 L CCCC DDDDDDDDD 010000100 LOCKRET D/# (waits for hub) --L- 1111111 00 L CCCC DDDDDDDDD 010000101 RDWIDE D/PTRA/PTRB (waits for hub) --L- 1111111 00 L CCCC DDDDDDDDD 010000110 RDWIDEC D/PTRA/PTRB (waits for hub if dcache miss) --L- 1111111 00 L CCCC DDDDDDDDD 010000111 RDWIDEQ D/PTRA/PTRB (waits for hub, doesn't affect dcache address/valid, waits 3 extra clocks) ZCL- 1111111 ZC L CCCC DDDDDDDDD 010001000 GETP D/# (pin into !Z/C via WZ/WC) ZCL- 1111111 ZC L CCCC DDDDDDDDD 010001001 GETNP D/# (pin into Z/!C via WZ/WC) -CL- 1111111 0C L CCCC DDDDDDDDD 010001010 SEROUTA D/# (waits for tx if single-task, loops if multi-task, releases if WC) -CL- 1111111 0C L CCCC DDDDDDDDD 010001011 SEROUTB D/# (waits for tx if single-task, loops if multi-task, releases if WC) -CL- 1111111 0C L CCCC DDDDDDDDD 010001100 CMPCNT D/# (subtracts D from CNT, then CNTX if same thread) -CL- 1111111 0C L CCCC DDDDDDDDD 010001101 WAITPX D/# (waits for any edge, +CNT if WC) -CL- 1111111 0C L CCCC DDDDDDDDD 010001110 WAITPR D/# (waits for pos edge, +CNT if WC) -CL- 1111111 0C L CCCC DDDDDDDDD 010001111 WAITPF D/# (waits for neg edge, +CNT if WC) --L- 1111111 00 L CCCC DDDDDDDDD 010010000 PUSH D/# (pushes into task's 4-level stack) ZCL- 1111111 ZC L CCCC DDDDDDDDD 010010001 SETZC D/# (D[1:0] into Z/C via WZ/WC) --L- 1111111 00 L CCCC DDDDDDDDD 010010010 SETXCH D/# --L- 1111111 00 L CCCC DDDDDDDDD 010010011 SETTASK D/# --L- 1111111 00 L CCCC DDDDDDDDD 010010100 SETRACE D/# --L- 1111111 00 L CCCC DDDDDDDDD 010010101 SARACCA D/# (waits for mac) --L- 1111111 00 L CCCC DDDDDDDDD 010010110 SARACCB D/# (waits for mac) --L- 1111111 00 L CCCC DDDDDDDDD 010010111 SARACCS D/# (waits for mac) --L- 1111111 00 L CCCC DDDDDDDDD 010011000 SETPTRA D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011001 SETPTRB D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011010 ADDPTRA D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011011 ADDPTRB D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011100 SUBPTRA D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011101 SUBPTRB D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011110 SETWIDE D/# --L- 1111111 00 L CCCC DDDDDDDDD 010011111 SETWIDZ D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100000 SETPTRX D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100001 SETPTRY D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100010 ADDPTRX D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100011 ADDPTRY D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100100 SUBPTRX D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100101 SUBPTRY D/# --L- 1111111 00 L CCCC DDDDDDDDD 010100110 PASSCNT D/# (loops if (CNT - D) msb set) --L- 1111111 00 L CCCC DDDDDDDDD 010100111 WAIT D/# (waits 1+ clocks, 0 same as 1) --L- 1111111 00 L CCCC DDDDDDDDD 010101000 OFFP D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101001 NOTP D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101010 CLRP D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101011 SETP D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101100 SETPC D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101101 SETPNC D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101110 SETPZ D/# --L- 1111111 00 L CCCC DDDDDDDDD 010101111 SETPNZ D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110000 DIV64D D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110001 SQRT32 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110010 QLOG D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110011 QEXP D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110100 SETQI D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110101 SETQZ D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110110 CFGDACS D/# --L- 1111111 00 L CCCC DDDDDDDDD 010110111 SETDACS D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111000 CFGDAC0 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111001 CFGDAC1 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111010 CFGDAC2 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111011 CFGDAC3 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111100 SETDAC0 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111101 SETDAC1 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111110 SETDAC2 D/# --L- 1111111 00 L CCCC DDDDDDDDD 010111111 SETDAC3 D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000000 SETCTRA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000001 SETWAVA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000010 SETFRQA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000011 SETPHSA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000100 ADDPHSA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000101 SUBPHSA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000110 SETVID D/# --L- 1111111 00 L CCCC DDDDDDDDD 011000111 SETVIDY D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001000 SETCTRB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001001 SETWAVB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001010 SETFRQB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001011 SETPHSB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001100 ADDPHSB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001101 SUBPHSB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001110 SETVIDI D/# --L- 1111111 00 L CCCC DDDDDDDDD 011001111 SETVIDQ D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010000 SETPIX D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010001 SETPIXZ D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010010 SETPIXU D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010011 SETPIXV D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010100 SETPIXA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010101 SETPIXR D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010110 SETPIXG D/# --L- 1111111 00 L CCCC DDDDDDDDD 011010111 SETPIXB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011011000 SETPORA D/# --L- 1111111 00 L CCCC DDDDDDDDD 011011001 SETPORB D/# --L- 1111111 00 L CCCC DDDDDDDDD 011011010 SETPORC D/# --L- 1111111 00 L CCCC DDDDDDDDD 011011011 SETPORD D/# --L- 1111111 00 L CCCC DDDDDDDDD 011011100 RDWIDEA D/#1..512 --L- 1111111 00 L CCCC DDDDDDDDD 011011101 RDWIDEB D/#1..512 --L- 1111111 00 L CCCC DDDDDDDDD 011011110 WRWIDEA D/#1..512 --L- 1111111 00 L CCCC DDDDDDDDD 011011111 WRWIDEB D/#1..512 --L- 1111111 00 L CCCC DDDDDDDDD 011100000 JMPT0 D/# --L- 1111111 00 L CCCC DDDDDDDDD 011100001 JMPT1 D/# --L- 1111111 00 L CCCC DDDDDDDDD 011100010 JMPT2 D/# --L- 1111111 00 L CCCC DDDDDDDDD 011100011 JMPT3 D/# --L- 1111111 00 L CCCC DDDDDDDDD 011100100 PUSHT0 D/# (pushes into task 0's 4-level stack) --L- 1111111 00 L CCCC DDDDDDDDD 011100101 PUSHT1 D/# (pushes into task 1's 4-level stack) --L- 1111111 00 L CCCC DDDDDDDDD 011100110 PUSHT2 D/# (pushes into task 2's 4-level stack) --L- 1111111 00 L CCCC DDDDDDDDD 011100111 PUSHT3 D/# (pushes into task 3's 4-level stack) --L- wrD 1111111 ZC L CCCC DDDDDDDDD 011101000 COGNEW D/# (waits for hub) --L- wrD 1111111 ZC L CCCC DDDDDDDDD 011101001 COGNEWX D/# (waits for hub) --R- 1111111 ZC x CCCC DDDDDDDDD 100000000 LOCPTRA D (PTRA = {D[15:0],%00}) (D[31:30] into Z/C via WZ/WC for LOCPTRA..CALLYD D) --R- 1111111 ZC x CCCC DDDDDDDDD 100000001 LOCPTRB D (PTRB = {D[15:0],%00}) --R- 1111111 ZC x CCCC DDDDDDDDD 100000010 JMP D --R- 1111111 ZC x CCCC DDDDDDDDD 100000011 JMPD D --R- wr0 1111111 ZC x CCCC DDDDDDDDD 100000100 LINK D (jump, write {Z,C,%00000000000000,P} to $000) --R- wr0 1111111 ZC x CCCC DDDDDDDDD 100000101 LINKD D --R- 1111111 ZC x CCCC DDDDDDDDD 100000110 CALL D --R- 1111111 ZC x CCCC DDDDDDDDD 100000111 CALLD D --R- 1111111 ZC x CCCC DDDDDDDDD 100001000 CALLA D --R- 1111111 ZC x CCCC DDDDDDDDD 100001001 CALLAD D --R- 1111111 ZC x CCCC DDDDDDDDD 100001010 CALLB D --R- 1111111 ZC x CCCC DDDDDDDDD 100001011 CALLBD D --R- 1111111 ZC x CCCC DDDDDDDDD 100001100 CALLX D --R- 1111111 ZC x CCCC DDDDDDDDD 100001101 CALLXD D --R- 1111111 ZC x CCCC DDDDDDDDD 100001110 CALLY D --R- 1111111 ZC x CCCC DDDDDDDDD 100001111 CALLYD D --R- 1111111 00 x CCCC DDDDDDDDD 100010000 LODINDA D --R- 1111111 00 x CCCC DDDDDDDDD 100010001 LODINDB D ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000000 RETA ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000001 RETAD ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000010 RETB ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000011 RETBD ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000100 RETX ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000101 RETXD ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000110 RETY ZC-- 1111111 ZC x CCCC xxxxxxxxx 110000111 RETYD ZC-- 1111111 ZC x CCCC xxxxxxxxx 110001000 RET ZC-- 1111111 ZC x CCCC xxxxxxxxx 110001001 RETD ZC-- 1111111 ZC x CCCC xxxxxxxxx 110001010 POLCTRA (ctra-rollover into !Z/C) ZC-- 1111111 ZC x CCCC xxxxxxxxx 110001011 POLCTRB (ctra-rollover into !Z/C) ZC-- 1111111 ZC x CCCC xxxxxxxxx 110001100 POLVID (vid-ready into !Z/C) ---- 1111111 00 x CCCC xxxxxxxxx 110001101 CAPCTRA ---- 1111111 00 x CCCC xxxxxxxxx 110001110 CAPCTRB ---- 1111111 00 x CCCC xxxxxxxxx 110001111 CAPCTRS ---- 1111111 00 x CCCC xxxxxxxxx 110010000 SETPIXW ---- 1111111 00 x CCCC xxxxxxxxx 110010001 CLRACCA ---- 1111111 00 x CCCC xxxxxxxxx 110010010 CLRACCB ---- 1111111 00 x CCCC xxxxxxxxx 110010011 CLRACCS ZC-- 1111111 ZC x CCCC xxxxxxxxx 110010100 CHKPTRX ZC-- 1111111 ZC x CCCC xxxxxxxxx 110010101 CHKPTRY ---- 1111111 00 x CCCC xxxxxxxxx 110010110 SYNCTRA (waits for ctra if single-task, loops if multi-task)) ---- 1111111 00 x CCCC xxxxxxxxx 110010111 SYNCTRB (waits for ctrb if single-task, loops if multi-task)) ---- 1111111 00 x CCCC xxxxxxxxx 110011000 DCACHEX ---- 1111111 00 x CCCC xxxxxxxxx 110011001 ICACHEX ---- 1111111 00 x CCCC xxxxxxxxx 110011010 ICACHEP ---- 1111111 00 x CCCC xxxxxxxxx 110011011 ICACHEN ---- 1111111 00 x 0000 xxxxxxxxx 110011100 TLOCK ---- 1111111 00 x 0000 xxxxxxxxx 110011101 TFREE ---- 1111111 00 x 0000 xxxxxxxxx 110011110 LOADT3 ---- 1111111 00 x 0000 xxxxxxxxx 110011111 SAVET3 x = don't care, use 0 --------------------------------------------------------------------------------------------------------------------- Z effect ------------------------------------------------------------------------------------------ 0 <none> 1 wz C effect ------------------------------------------------------------------------------------------ 0 <none> 1 wc L DDDDDDDDD destination operand ------------------------------------------------------------------------------------------ 0/na DDDDDDDDD register 1 #DDDDDDDDD immediate, zero-extended I SSSSSSSSS source operand ------------------------------------------------------------------------------------------ 0/na SSSSSSSSS register 1 #SSSSSSSSS immediate, zero-extended CCCC condition (easier-to-read list) ------------------------------------------------------------------------------------------ 0000 never 1111 always (default) 0001 nc & nz 1100 if_c if_b 0010 nc & z 0011 if_nc if_ae 0011 nc 1010 if_z if_e 0100 c & nz 0101 if_nz if_ne 0101 nz 1000 if_c_and_z if_z_and_c 0110 c <> z 0100 if_c_and_nz if_nz_and_c 0111 nc | nz 0010 if_nc_and_z if_z_and_nc 1000 c & z 0001 if_nc_and_nz if_nz_and_nc if_a 1001 c = z 1110 if_c_or_z if_z_or_c if_be 1010 z 1101 if_c_or_nz if_nz_or_c 1011 nc | z 1011 if_nc_or_z if_z_or_nc 1100 c 0111 if_nc_or_nz if_nz_or_nc 1101 c | nz 1001 if_c_eq_z if_z_eq_c 1110 c | z 0110 if_c_ne_z if_z_ne_c 1111 always 0000 never CCCC inda/indb - CCCC=1111 after stage 2 of pipeline if inda/indb used (indx=inda/indb) ------------------------------------------------------------------------------------------ xx00 source indx xx01 source indx++ xx10 source indx-- xx11 source ++indx 00xx destination indx 01xx destination indx++ 10xx destination indx-- 11xx destination ++indxVGA and PS2 keyboard/mouse was not general purpose, but P1 was wonderful because of them.
I think P2 would be awesome if you can make USB as easy as current serial transceivers.
old way:
new way:
Thanks,
electrodude
EDIT: nr would only work inside a tlock or in a single-tasked program, making the mov method easier for multitasking. My nr instruction is still easier for singletasking.
AUGNR 'next instruction does not write out the result, only affects Z & C flags according to WZ & WC
Works just like AUGS & AUGD.
This could work, per task, but could you give me an instruction sequence that would benefit from this feature? I was just looking at the instruction set and I don't see any obvious cases where blocking the result writing would gain anything. If you can convince me, I'll do it. And better yet, we could have an instruction that actually redirects the result writing to another register 'NEXTWR D/#'.
Interesting idea! Would remove the need for temp registers in a lot of code.
Edit: One use for that could be something like:
NEXTWR c MUL a,bOn P1 I often used instructions like
SHR/SHL/ROR/ROL/RLC/RCR/AND/XOR <reg>,<#nnn NR WZ,WC 'check bit(s)
We can now check a bit using TESTB but it would mostly use a reg. There are cases where the NR was quite useful. There are of course ways around this, using a temp register.
IMHO a single AUGNR would be most useful. To work just like AUGS and AUGD does. This way, all the standard instructions such as the above, plus things like NEG, ADD, SUB, etc could be made to work using the AUGNR preceding the instruction. Would this be difficult?
Another instruction I mentioned a little earlier was to put D[1:0 + offset] into Z & C using wz and wc. By rotating D to the right #offset times, we could use any bit pair to set Z & C flags. This permits full 4 way decoding quickly. I thought that SETZC could be extended to be SETZC D/#,#0..31 using say
ZCL- 1111111 ZC L CCCC DDDDDDDDD 1111nnnnn SETZC D/#,#nnnnn 'where nnnnn shifts D right 0..31 places (default is 30). Note D is not written.
Postedit:
NEXTWR D/#
Could be extremely useful for giving a separate result from 2 inputs (D & S). Maybe we could utilise the special register $1F1 to mean NR.
IMHO this would be more versatile than AUGNR. Maybe AUGDEST might be a better name (since it is like AUGS and AUGD).
Does SETMASK, WIDEBM, WIDEWM and WIDELM still exist?
See here
Only these:
WRWIDE S/PTRA/PTRB
WRWIDEM D/#,S/PTRA/PTRB
WRWIDEM lets you specify a 32-mask in D/# where 1's inhibit individual byte writes within the 32-byte WIDE. So, by making it atomic, we don't need SETMASK.
RESD #C
MUL A,B
...writes A*B to C
RESD #1
LINK #address16
...writes the return address to $001 instead of $000
RESD A
...indirection for writes
Do you have the opcode for that?