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Propeller II update - BLOG - Page 134 — Parallax Forums

Propeller II update - BLOG

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  • cgraceycgracey Posts: 14,155
    edited 2013-12-09 15:05
    Ken Gracey wrote: »
    I paid a visit to our manufacturing to see what kind of tooling investment we have in the Terasic DE2-115 Adapter Board. Answer: not much. Though our stencil is metal it's also a one-up and there's little investment in the PnP programming due to the small number of parts, so I can easily make PCB changes. Believe it or not, this is the first time I've had a close-up look at this board - Chip handled it sorta informally so it didn't get a Parallax part number and the benefits of our formalized business tools that keep making whatever we ordered until somebody tells the machines and people to stop. I can tell this is his design because it has no mechanical mounting holes [like the original Propeller Demo Board . . .hope he doesn't read this!].

    Any more changes other than widening the board to accommodate two mounting holes and hardware for .020" spacers?

    What about this vertical PropPlug header? If we widen the PCB and move the header a little north then I could replace it with a right-angle connector. However, the board would need to be widened enough so that the right-angle header is entirely within the confines of the PCB perimeter (we send populated boards through a pizza cutter).

    Thanks,

    Ken Gracey

    Attachment not found.

    Ken, any chance we could get those boards cheaply enough from Terasic so that we could bundle them with our Prop2 add-on board for their retail price of $599?

    Cyclone V offers better performance, but the Cyclone IV-based DE2-115 features SDRAM, which the Prop2 will use. If we don't use the DE2-115, we'd need to build our own FPGA board using the Cyclone V -A7 chip.
  • jmgjmg Posts: 15,173
    edited 2013-12-09 15:17
    Ken Gracey wrote: »
    Any more changes other than widening the board to accommodate two mounting holes and hardware for .020" spacers?

    I'd check with Terasic and Altera, on upcoming Cyclone V offerings.

    I see a Terasic Cyclone V PCB for $179, so check the headers on that, and maybe a dual-pin-out PCB can come ?
  • Ken GraceyKen Gracey Posts: 7,392
    edited 2013-12-09 15:18
    cgracey wrote: »
    Ken, any chance we could get those boards cheaply enough from Terasic so that we could bundle them with our Prop2 add-on board for their retail price of $599?

    Cyclone V offers better performance, but the Cyclone IV-based DE2-115 features SDRAM, which the Prop2 will use. If we don't use the DE2-115, we'd need to build our own FPGA board using the Cyclone V -A7 chip.

    Chip,

    If you are referring to this Cyclone V board https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=741 or any other Terasic-sold board that is actually Altera's development kit (noted by a part number that begins with a "T") then no, we cannot resell it. An agreement between Altera and their distributor(s) prevents this arrangement.

    The DE2-115 is a Terasic board and yes, we can resell it. We're just getting our costs and agreement worked out right now. We could certainly try to include the DE2-115 Adapter Board in the $599 package, depending on our costs of both boards. But I still don't know our DE2-115 costs from Terasic or the costs of building the DE2-115 Adapter Board.

    We could certainly start with the DE2-115 combination and design a Cyclone V-A7 board concurrently for future release. We'll make it easier for early P2 adopters to code their products, for C compiler guys, retro gamers, and anybody else who wants to get started. I haven't seen what's involved with the steps of installing software (that big Quartus package?) and actually downloading the P2 core, but we'd document that as well.

    Ken Gracey
  • jmgjmg Posts: 15,173
    edited 2013-12-09 15:22
    cgracey wrote: »
    Cyclone V offers better performance, but the Cyclone IV-based DE2-115 features SDRAM, which the Prop2 will use. If we don't use the DE2-115, we'd need to build our own FPGA board using the Cyclone V -A7 chip.

    Since you already talk with Terasic, and they have FPGA boards on either side of a 'Prop 2 sweet spot', you could start on their
    Cyclone V GX Starter Kit ($179), and find what volumes they need to either do a custom-stuff of that, or a PCB change of that ?

    The Arrow BeMicro CV ($49) seems to have become harder to get ? - either huge demand, or some issues ?
  • jmgjmg Posts: 15,173
    edited 2013-12-09 15:26
    Ken Gracey wrote: »
    Chip,

    If you are referring to this Cyclone V board https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=741 or any other Terasic-sold board that is actually Altera's development kit (noted by a part number that begins with a "T") then no, we cannot resell it. An agreement between Altera and their distributor(s) prevents this arrangement.

    The DE2-115 is a Terasic board and yes, we can resell it.

    If you look at
    http://www.altera.com/products/devkits/cyclone-index.jsp
    Is the Provider Column what you mean here ?

    There is already a $179 CV board, listed with Terasic as provider.
  • Ken GraceyKen Gracey Posts: 7,392
    edited 2013-12-09 15:28
    jmg wrote: »
    I'd check with Terasic and Altera, on upcoming Cyclone V offerings.

    I see a Terasic Cyclone V PCB for $179, so check the headers on that, and maybe a dual-pin-out PCB can come ?

    OK, we'll give that a look too. I'll add that to Daniel's list to review.

    One more separate thought about these FPGA boards unrelated to your reply - we've made our own FPGA boards before and I remember it being a constant chase to keep up with Altera's latest releases. Making our own FPGA board could lower costs, but it also means we have excess inventory every time we upgrade the FPGA to the latest model. At a few hundred dollars a piece, leftover parts from a single production run can outweigh all gross profit associated with the prior builds. And if these new Altera releases are fast enough, making FPGA boards is like chasing a rabbit down a hole (instead of through a lush, green forest!). We claw at the dirt, digging deeper, kicking scrap FPGAs up behind us! I'd at least like the FPGA stuff to be able to pay for itself. This is a benefit of being able to sell somebody else's FPGA board vs. making our own.

    Without a doubt, it's far more fun, tidy and inspiring to have our own FPGA boards. Talk about beautiful black stallions - look at the cool stuff Chip designed almost ten years ago.

    Cyclone324.jpg
    StratixSmartPack.jpg
    600 x 582 - 114K
    450 x 470 - 107K
  • jmgjmg Posts: 15,173
    edited 2013-12-09 15:35
    Ken Gracey wrote: »
    One more separate thought about these FPGA boards unrelated to your reply - we've made our own FPGA boards before and I remember it being a constant chase to keep up with Altera's latest releases. Making our own FPGA board could lower costs, but it also means we have excess inventory every time we upgrade the FPGA to the latest model. At a few hundred dollars a piece, leftover parts from a single production run can outweigh all gross profit associated with the prior builds. And if these new Altera releases are fast enough, making FPGA boards is like chasing a rabbit down a hole (instead of through a lush, green forest!). We claw at the dirt, digging deeper, kicking scrap FPGAs up behind us! I'd at least like the FPGA stuff to be able to pay for itself. This is a benefit of being able to sell somebody else's FPGA board vs. making our own.

    Exactly, see my other post, where I suggest talking with Terasic re what else they have in the pipelines, and on build variants of what they have already ?

    To underline your moving target point, the CV board,is already cheaper than the C IV one.
  • ColeyColey Posts: 1,110
    edited 2013-12-09 15:37
    +1

    I have a sticky note tower underneath mine to keep it level (and the connectors safe) that I hate.

    This is what supports mine ;-)

    2013-12-09 22.20.43.jpg
    2013-12-09 22.21.02.jpg
    2013-12-09 22.21.12.jpg



    Here is the design file in case anyone can make use of it DE2 P2 DAC Carrier.zip

    It's only a quick 'n dirty fix but it works really well :smile:
    816 x 612 - 202K
    816 x 612 - 162K
    816 x 612 - 165K
  • Ken GraceyKen Gracey Posts: 7,392
    edited 2013-12-09 15:39
    Happy to take post 4,000 for making a subtle reminder. If we value each post on this thread at $1,000 then you'll approximate our total P2 investment up to last summer.

    Looking forward to P2!

    Ken Gracey
  • Ken GraceyKen Gracey Posts: 7,392
    edited 2013-12-09 15:45
    jmg wrote: »
    Exactly, see my other post, where I suggest talking with Terasic re what else they have in the pipelines, and on build variants of what they have already ?

    To underline your moving target point, the CV board,is already cheaper than the C IV one.

    Got it, jmg. I was posting without going back to read some replies. Yes, as it's almost morning in Taipei I will contact them to discuss the possibility of having them make a Cyclone V board for Parallax. Sometimes, once we start communicating specs and going through design iterations it is best to make it on our own (unless they have a much lower cost on the FPGA chips that justifies the whole effort). This is a viable suggestion and worth looking into, especially if they have additional channels to justify the NRE.
  • Ym2413aYm2413a Posts: 630
    edited 2013-12-09 15:45
    Hey guys, once you get the new wave of FPGA boards ready. Please let me know. I want to get a jump start on the P2 Development as well. : ]
    Right now I'm not sure if the FPGA image floating around is the most recent one with all the Op-Code changes or if it's out dated.

    Thanks!
    --Andrew L. Arsenault.
  • jmgjmg Posts: 15,173
    edited 2013-12-09 16:02
    Ken Gracey wrote: »
    Got it, jmg. I was posting without going back to read some replies. Yes, as it's almost morning in Taipei I will contact them to discuss the possibility of having them make a Cyclone V board for Parallax. Sometimes, once we start communicating specs and going through design iterations it is best to make it on our own (unless they have a much lower cost on the FPGA chips that justifies the whole effort). This is a viable suggestion and worth looking into, especially if they have additional channels to justify the NRE.

    Often FPGA's have common footprints, so you may be able to have something as simple as a different FPGA mounted.

    Meanwhile, getting code running on their standard IV and V parts, is a good first step, and I'd be cautious to not over-stock on DE2-115.
  • Ken GraceyKen Gracey Posts: 7,392
    edited 2013-12-09 16:05
    jmg wrote: »
    Often FPGA's have common footprints, so you may be able to have something as simple as a different FPGA mounted.

    Meanwhile, getting code running on their standard IV and V parts, is a good first step, and I'd be cautious to not over-stock on DE2-115.

    OK, will take both points into account. Thanks again.
  • TubularTubular Posts: 4,702
    edited 2013-12-09 16:15
    Coley, that's brilliant, thanks for that. I was just thinking something 3d could solve this issue without a pcb board revision, and hey presto there it is

    Coley wrote: »
    This is what supports mine ;-)

    2013-12-09 22.20.43.jpg
    2013-12-09 22.21.02.jpg
    2013-12-09 22.21.12.jpg



    Here is the design file in case anyone can make use of it DE2 P2 DAC Carrier.zip

    It's only a quick 'n dirty fix but it works really well :smile:
  • TubularTubular Posts: 4,702
    edited 2013-12-09 16:26
    Ken Gracey wrote: »
    I haven't seen what's involved with the steps of installing software (that big Quartus package?) and actually downloading the P2 core, but we'd document that as well.

    Ken the good news is the programmer part of the package (Quartus Programmer) is available separately. It's still a large download, but doesn't have nearly the complexity of the whole giant Altera package.
  • Cluso99Cluso99 Posts: 18,069
    edited 2013-12-09 16:46
    Ken,
    If you contemplate building an FPGA board yourselves, I spent some time examining the Cyclone V parts.
    The 23x23 484 pin Cyclone V base chips use the same pinout (jsut some unused). This means you could produce 2 variants, one much cheaper 2 cog version and another for 6-8 cogs.
    I am not at home for a couple of days, so I will email my info when I get back. I am happy to help.

    You would need to check that Altera will supply their software free/cheap for these 2 Cyclone V chips as this would otherwise be a killer.

    On the pcb would be a usb to download fpga code and then possibly also do the propplug usb interface. May need separate USB ports? Else a Propplug header with better mechanicals than we have on the expansion DE0 board.

    Also requires the config flash (fpga) and the SPI Flash for the P2. Also, the SDRAM so we can simulate it being connected to the P2.

    And lastly, the DACs for video. And a few leds and switches plus reset switch might be in order.
  • RamonRamon Posts: 484
    edited 2013-12-10 01:16
    Ken Gracey wrote: »
    Yes, as it's almost morning in Taipei I will contact them to discuss the possibility of having them make a Cyclone V board for Parallax.

    Ken, welcome to Taiwan. Two days ago we had a sunny day (77F / 25C), but now is getting colder.

    To avoid you to see old post, some toughs about Cyclone V development boards:

    1) PACKAGING: We found that those FPGA in 484 BGA 23x23 or 19x19 allow vertical migration: different size (number of Logic Elements / LE) but same pinout, so it reduces layout NRE cost.

    2) FPGA VERSION: Optimum version is -A7. The biggest (149000 logic elements) that still can be used with free version of Quartus.

    We found that Cyclone V 5CEFA2 (25K LE) and 5CEFA4 (49K LE) has the same pinout. Higher density 5CEFA5 and 5CEFA7 (149K LE) seems to have different pinout than 5CEFA2. The highest density Cyclone V (A9) cannot be used in free quartus Edition. So we cannot do full emulation of eight cog P2 (maybe just up to 6 cogs)

    3) SDRAM vs DDR: Current P2 development is done with SDRAM in mind. Almost all recent FPGA development boards uses DDR. It would be nice to have a dual SDRAM/DDR board or user selectable/configurable option via external memory module. Problem: this doesn't fit with low cost boards like DE0-nano (uses SDRAM and cost $79) or Bemicro CV (uses DDR and cost $49)

    My personal opinion about development boards: I would prefer a powerful FPGA (-A7 version) and low cost board like DE0-nano ($79) or Bemicro CV ($49) to a powerfull FPGA with a lot of unused components (like $179 DE-115). Maybe a poll question could give the answer to what is worth.

    Also, a personal inquiry related to accesories/add-on board: a SD card is not enough, please think also about a compact flash (or 40 pin IDE/ATA) module or add-on board. (This was discussed in other thread.)

    I think that a DE0 nano version, with Cyclone A7 FPGA (149K LE), user configurable SDRAM or DDR module, and low cost could be of great benefit for both Parallax and Terasic.
  • Heater.Heater. Posts: 21,230
    edited 2013-12-10 01:55
    Ken,
    If we value each post on this thread at $1,000 then you'll approximate our total P2 investment up to last summer.
    Seriously ouch!

    I'm speechless.
  • LeonLeon Posts: 7,620
    edited 2013-12-10 02:14
    Cyclone V boards tend to use DDR3 RAMs, which aren't supported by P2. It probably doesn't matter for simulation purposes, though.
  • roglohrogloh Posts: 5,790
    edited 2013-12-10 02:21
    Ken Gracey wrote: »
    Happy to take post 4,000 for making a subtle reminder. If we value each post on this thread at $1,000 then you'll approximate our total P2 investment up to last summer.

    Looking forward to P2!

    Ken Gracey

    Yeah you certainly need quite a lot of money for doing an ASIC. Any rough % breakdown estimates of where it was mainly spent? Just for interest. ie

    R&D costs/salaries,
    S/W & H/W tools,
    Silicon prototyping & testing,
    Marketing,
    Other major costs?

    It's been years of development so I imagine R&D was a pretty big part to date, transitioning now into some larger silicon costs.
  • cgraceycgracey Posts: 14,155
    edited 2013-12-10 02:33
    rogloh wrote: »
    Yeah you certainly need quite a lot of money for doing an ASIC. Any rough % breakdown estimates of where it was mainly spent? Just for interest. ie

    R&D costs/salaries,
    S/W & H/W tools,
    Silicon prototyping & testing,
    Marketing,
    Other major costs?

    It's been years of development so I imagine R&D was a pretty big part to date, transitioning now into some larger silicon costs.

    The costs were in descending order as you listed them.
  • roglohrogloh Posts: 5,790
    edited 2013-12-10 02:36
    Thanks Chip.
  • BaggersBaggers Posts: 3,019
    edited 2013-12-11 08:12
    Ken Gracey wrote: »
    I think you're referring to the DE2-115 I brought you two years back? If so, we should be in a position to service these pretty soon as a Terasic supplier of this particular board. I am also restarting the DE2-115 adapter board manufacturing. These two efforts should keep your FPGA boards functioning.
    Cheers Ken, that would be awesome, and yes, it was the DE2-115 you sent over :) I'll send it up to Coley first, see if it's a quick fix, if not I'll let you know.

    Coley, I'll email you.
  • Ahle2Ahle2 Posts: 1,179
    edited 2013-12-11 11:46
    Chip,
    Did you ever think more about my proposed mux/demux instructions (post 1216183) or did you deem them to slow to be useful. Just curious. :)

    /Johannes
  • jmgjmg Posts: 15,173
    edited 2013-12-11 13:59
    Leon wrote: »
    Cyclone V boards tend to use DDR3 RAMs, which aren't supported by P2. It probably doesn't matter for simulation purposes, though.

    I'm wondering the the P2 Port IO groups can have differing IO supply voltage ?

    - and if a DDR2 or DDR3 device can be connected, for SW access, but I think those top-end DDR memories have clock-compensating PLL's so they will expect a hardware (and limited range) CLK source.

    SDRAM seems to still have a pulse - Digikey yields this
    Part Number	  Description	               Qty Avl	USD	@ qty	Voltage        Temperature	Package
    AS4C1M16S-7TCN	  SDRAM 16MBIT 143MHZ 50TSOP	319	0.80784	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    W9816G6IH-6	  SDRAM 16MBIT 166MHZ 50TSOP	600	0.87120	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    AS4C4M16S-7TCN	  SDRAM 64MBIT 143MHZ 54TSOP	1300	0.94248	1000	3 V ~ 3.6 V	0°C ~ 70°C	54-TSOP II
    W9816G6IH-6I	  SDRAM 16MBIT 166MHZ 50TSOP	617	0.96624	1000	3 V ~ 3.6 V	-40°C ~ 85°C	50-TSOP II
    AS4C4M16S-6TIN	  SDRAM 64MBIT 166MHZ 54TSOP	186	1.07712	1000	3 V ~ 3.6 V	-40°C ~ 85°C	54-TSOP II
    AS4C2M32S-7TCN	  SDRAM 64MBIT 143MHZ 86TSOP	299	1.26820	1000	3 V ~ 3.6 V	0°C ~ 70°C	86-TSOP II
    IS42S16100F-7TL	  SDRAM 16MBIT 143MHZ 50TSOP	223	1.34640	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    IS42S16100E-7TL	  SDRAM 16MBIT 143MHZ 50TSOP	463	1.42560	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    
    

    The Commercial AS4C4M16S-7TCN & Industrial + faster AS4C4M16S-6TIN seem best-value-fits to P2 ?
  • evanhevanh Posts: 15,919
    edited 2013-12-11 14:01
    Ahle2 wrote: »
    Did you ever think more about my proposed mux/demux instructions (post 1216183) ...

    http://forums.parallax.com/showthread.php/125543-Propeller-II-update-BLOG?p=1216183&viewfull=1#post1216183
  • cgraceycgracey Posts: 14,155
    edited 2013-12-11 14:33
    evanh wrote: »

    Thanks for the link.

    I remember this now. If it could magically fill up any arbitrary set of holes, it would be super useful, but that would take a lot of gate time, as the hole-seeking would be sequential. If it were a contiguous field of bits, without interruption, it would be a lot simpler. It could be done.

    I love the idea of ANY arbitrary bits. That would be the ultimate, but maybe not practical.
  • cgraceycgracey Posts: 14,155
    edited 2013-12-11 14:35
    jmg wrote: »
    I'm wondering the the P2 Port IO groups can have differing IO supply voltage ?

    - and if a DDR2 or DDR3 device can be connected, for SW access, but I think those top-end DDR memories have clock-compensating PLL's so they will expect a hardware (and limited range) CLK source.

    SDRAM seems to still have a pulse - Digikey yields this
    Part Number	  Description	               Qty Avl	USD	@ qty	Voltage        Temperature	Package
    AS4C1M16S-7TCN	  SDRAM 16MBIT 143MHZ 50TSOP	319	0.80784	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    W9816G6IH-6	  SDRAM 16MBIT 166MHZ 50TSOP	600	0.87120	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    AS4C4M16S-7TCN	  SDRAM 64MBIT 143MHZ 54TSOP	1300	0.94248	1000	3 V ~ 3.6 V	0°C ~ 70°C	54-TSOP II
    W9816G6IH-6I	  SDRAM 16MBIT 166MHZ 50TSOP	617	0.96624	1000	3 V ~ 3.6 V	-40°C ~ 85°C	50-TSOP II
    AS4C4M16S-6TIN	  SDRAM 64MBIT 166MHZ 54TSOP	186	1.07712	1000	3 V ~ 3.6 V	-40°C ~ 85°C	54-TSOP II
    AS4C2M32S-7TCN	  SDRAM 64MBIT 143MHZ 86TSOP	299	1.26820	1000	3 V ~ 3.6 V	0°C ~ 70°C	86-TSOP II
    IS42S16100F-7TL	  SDRAM 16MBIT 143MHZ 50TSOP	223	1.34640	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    IS42S16100E-7TL	  SDRAM 16MBIT 143MHZ 50TSOP	463	1.42560	1000	3 V ~ 3.6 V	0°C ~ 70°C	50-TSOP II
    
    

    The Commercial AS4C4M16S-7TCN & Industrial + faster AS4C4M16S-6TIN seem best-value-fits to P2 ?

    That would work, but for double the $1 price, you could get 4x the memory in a 256MB part.
  • jmgjmg Posts: 15,173
    edited 2013-12-11 15:19
    cgracey wrote: »
    That would work, but for double the $1 price, you could get 4x the memory in a 256MB part.

    Yes, I've already added that 256MB choice to the LIST i did in the SDRAM thread.
    ( on the same scale it is $1.58525 @1000 for the commercial grade and $2.00000 @1000 for the faster, extended temp model.
  • cgraceycgracey Posts: 14,155
    edited 2013-12-11 15:44
    jmg wrote: »
    Yes, I've already added that 256MB choice to the LIST i did in the SDRAM thread.
    ( on the same scale it is $1.58525 @1000 for the commercial grade and $2.00000 @1000 for the faster, extended temp model.

    It really blows me away that for $1.58 you can buy 32MB of RAM! It seems like yesterday that 32KB cost twice that. And this is 333MB/s in one chip.
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