1) 64 bit cogs!
With 64 bit instructions, the 32 bits would easily allow adding 7 more bits to SRC and DST, for up to 64K 64 bit COG locations, and still leave 18 bits for other goodies.
2) 16 cogs
3) 1MB of hub memory, organized as 128K x 64
There are really many possible P2+ future paths. This big jump wishlist is more like P7 ?
Next iterations are more likely to be smaller steps, ie using the same process and same PAD Ring IP.
A large iteration (significant process shrink) is more likely to include RISC-V core(s?), and that drops the need for 16 COGs
ofcourse fast SPI-like modes for input and output, and addition of Manchester coding to allow at least 100BaseT
Quad and Octa SPI / HyperBUS etc modes to allow XIP could certainly be considered.
Allowing more transparent XIP eases pressure on Code memory.
The i.MX MCUs from NXP also make interesting reading, someone may do a module with one of those + P2, which also eases pressure on any P3..P7?
From NXP web, simplest variant : The i.MX RT1010 Features
Arm® Cortex®-M7 up to 500 MHz
Real-time, low-latency response as low as 20 ns
External memory interface options
80 LQFP packages for low-cost PCB designs
$0.99 suggested resale for 100 Ku
The trouble with trying to tack onto a really old thread is that we get caught off-guard not always realizing that it's an old thread, and then we start to respond to the old posts and go "doh".
So I would always recommend to start a new thread if the old one is years old.
I know that moderators can lock threads. Perhaps a good forum feature to have is for the forum to automatically lock threads which lay dormant for more than a few years?
We can always link to them for reference if need be. But then again, this kind of thing, although not unusual, rarely happens.
The trouble with trying to tack onto a really old thread is that we get caught off-guard not always realizing that it's an old thread, and then we start to respond to the old posts and go "doh".
So I would always recommend to start a new thread if the old one is years old.
I know that moderators can lock threads. Perhaps a good forum feature to have is for the forum to automatically lock threads which lay dormant for more than a few years?
We can always link to them for reference if need be. But then again, this kind of thing, although not unusual, rarely happens.
I know of one forum that throws up a red banner with a warning about the age of the thread.
Comments
Ray
There are really many possible P2+ future paths. This big jump wishlist is more like P7 ?
Next iterations are more likely to be smaller steps, ie using the same process and same PAD Ring IP.
A large iteration (significant process shrink) is more likely to include RISC-V core(s?), and that drops the need for 16 COGs
Quad and Octa SPI / HyperBUS etc modes to allow XIP could certainly be considered.
Allowing more transparent XIP eases pressure on Code memory.
The i.MX MCUs from NXP also make interesting reading, someone may do a module with one of those + P2, which also eases pressure on any P3..P7?
From NXP web, simplest variant :
The i.MX RT1010 Features
Arm® Cortex®-M7 up to 500 MHz
Real-time, low-latency response as low as 20 ns
External memory interface options
80 LQFP packages for low-cost PCB designs
$0.99 suggested resale for 100 Ku
It'd have been dead for over 10 years!
Kind regards, Samuel Lourenço
So I would always recommend to start a new thread if the old one is years old.
I know that moderators can lock threads. Perhaps a good forum feature to have is for the forum to automatically lock threads which lay dormant for more than a few years?
We can always link to them for reference if need be. But then again, this kind of thing, although not unusual, rarely happens.
But, I’ve been here a while...
And, I think P2 is pretty awesome.
I know of one forum that throws up a red banner with a warning about the age of the thread.