Thanks Chip. Here is what I understand the timing will be based on your internal gate delays and allowing for rise time of ~0.5ns due to loading.
So to take this a little further.
The pins PHYSICALLY change state near the start of the "R" cycle with the delay due to the internal gate delays from when the ALU writes the pins.
The pins are PHYSICALLY sampled near the end of the "S" cycle due to the internal gate delays before latching takes place at the start of the "D" (or end of the "S") cycle.
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Chip Gracey (Parallax) said...
Kuroneko, I am going to have to look at the HDL code to figure out why you are seeing this. I should have some explanation tonight.
Wouldn't you be outputting from the start of the phase (rising clock edge) and inputting (latching) at the end of the phase (rising clock edge of the next phase) ?
So in a Destination read, you would be selecting the register/cog ram (address) at the start of the "D" cycle and then allow for the internal gate delays, so latch the data at the end of the "D" cycle. This could explain the results kuroneko is seeing. In this instance, my timing above would be incorrect and the pins should be latched on clock 8 not 7.
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Cluso, I'm pretty sure that in any cycle, the cog RAM address is latched one clock before the RAM output data is latched. In the case of the write cycle, address AND data must be presented at the same clock edge. I'm going to have to look at the HDL code to remember properly.
Okay, looked at the HDL source and here is what happens:
········
Cog RAM
State·· R/W·· Address······· Data In···Data Out··········Other
0······R···· source········ -·········-················ -
1······ R···· destination··· -·········source············S register is latched
2······ R···· instruction··· -·········destination·······Final S·is mux'd and latched, D register is latched
3······ W···· destination··· result····instruction·······ALU settles with S/D inputs, result is written·to D register
So, this is a little different that what I have said before.
Kuroneko, this explains why you get those results.
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Chip Gracey
Parallax, Inc.
Post Edited (Chip Gracey (Parallax)) : 12/6/2009 8:03:22 AM GMT
There are some before-clock/after-clock distinctions that should be made:
- R/W, Addr, and Din will be latched at the END of the state. Dout, though, becomes available at the BEGINNING of the state. And, of course, the state advances with each rising edge of the clock.
- Latch I/S/D/src are inputs to the I/S/D/src latches, so they are captured at the END of the state.
It might be good to present this data so that the rising edges are denoted with vertical lines and your data names are right- or left-justified against them, so that it is obvious that some are inputs and others outputs of the flipflops.
Better put a few blanks lines before the line beginning with '·············· ALU········ W result'... (though I might be reading it wrong).
You might want to make some distinction between I/S/D/R sets, as the instruction fetch overlaps (ie I(n+1), R(n), S(n+1), D(n+1), where R means result to be written to D).
The bottom section, below the 80MHz clock line, I,d,S,D,e,R needs to shift right one clock. However, the 'Data Setup Time' is in the right position. If you want to post this comment section, I can make some changes to it that I might not have explained well enough.
I have attached the timing diagram. I think perhaps there should be 2 consecutive vertical arrows showing the latching followed by the incrementing, etc. Although they occur simultaneously,·owing to gate delays they latch different data (i.e. latching occurs before the increment filters through).
I have also attached a timing diagram for kuroneko's puzzle. Perhaps you could explain/fix the waitcnt timing implications·to the following jmp. I have "made" it fit the observed results but not sure if it is correct. (note the second part of his puzzle - the add cnt,%xxx ·is incorrect but I just hadn't considered that section properly and·will do this later)
Are the powers to be letting you out of your 'cage' to go to China late January?? *grin*
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Cluso99 said...
I have also attached a timing diagram for kuroneko's puzzle. Perhaps you could explain/fix the waitcnt timing implications to the following jmp. I have "made" it fit the observed results but not sure if it is correct.
With the minimum run-through time of 6 cycles (valid for waitpxx and waitcnt, haven't tested waitvid) I can see that either ina or cnt is looked at in the 4th (or 6th if you consider Id) cycle of the instruction (i.e. something like IdSDeL?R). Remember that e is busy with latching final source (mask/increment) and destination (pxx target/cnt target). So for waitcnt zero, #n the zero has to happen during e to be visible as input to L (for a run-through). If you go from there, the next instruction sees 5 to be sampled during e.
Disclaimer: This model explains my observations, but could be completely wrong [noparse]:)[/noparse]
Comments
So to take this a little further.
The pins PHYSICALLY change state near the start of the "R" cycle with the delay due to the internal gate delays from when the ALU writes the pins.
The pins are PHYSICALLY sampled near the end of the "S" cycle due to the internal gate delays before latching takes place at the start of the "D" (or end of the "S") cycle.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Post Edited (Cluso99) : 12/6/2009 6:22:32 AM GMT
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Chip Gracey
Parallax, Inc.
Wouldn't you be outputting from the start of the phase (rising clock edge) and inputting (latching) at the end of the phase (rising clock edge of the next phase) ?
So in a Destination read, you would be selecting the register/cog ram (address) at the start of the "D" cycle and then allow for the internal gate delays, so latch the data at the end of the "D" cycle. This could explain the results kuroneko is seeing. In this instance, my timing above would be incorrect and the pins should be latched on clock 8 not 7.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
········
Cog RAM
State·· R/W·· Address······· Data In···Data Out··········Other
0····· ·R···· source········ -·········-················ -
1······ R···· destination··· -·········source············S register is latched
2······ R···· instruction··· -·········destination·······Final S·is mux'd and latched, D register is latched
3······ W···· destination··· result····instruction·······ALU settles with S/D inputs, result is written·to D register
So, this is a little different that what I have said before.
Kuroneko, this explains why you get those results.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
Post Edited (Chip Gracey (Parallax)) : 12/6/2009 8:03:22 AM GMT
So is there a new consensus on my question 2 ? If so, could someone summarize the answer in simple terms?
Thanks.
In Time all infor on this topic is corrected.
CAN any of YOU write it in simpler for ..... AS errata to Propeller manual.
That information are much appreciated.
In advanced programing.
REGARDS
Christoffer J
You'll have three clocks' time, minus the internal propagation delays. So, at 80MHz, you'll have about 33ns (3 * 12.5ns - ~4.5ns).
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
That looks right.
There are some before-clock/after-clock distinctions that should be made:
- R/W, Addr, and Din will be latched at the END of the state. Dout, though, becomes available at the BEGINNING of the state. And, of course, the state advances with each rising edge of the clock.
- Latch I/S/D/src are inputs to the I/S/D/src latches, so they are captured at the END of the state.
It might be good to present this data so that the rising edges are denoted with vertical lines and your data names are right- or left-justified against them, so that it is obvious that some are inputs and others outputs of the flipflops.
Better put a few blanks lines before the line beginning with '·············· ALU········ W result'... (though I might be reading it wrong).
You might want to make some distinction between I/S/D/R sets, as the instruction fetch overlaps (ie I(n+1), R(n), S(n+1), D(n+1), where R means result to be written to D).
The bottom section, below the 80MHz clock line, I,d,S,D,e,R needs to shift right one clock. However, the 'Data Setup Time' is in the right position. If you want to post this comment section, I can make some changes to it that I might not have explained well enough.
Thanks for making this chart.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Chip Gracey
Parallax, Inc.
I have attached the timing diagram. I think perhaps there should be 2 consecutive vertical arrows showing the latching followed by the incrementing, etc. Although they occur simultaneously,·owing to gate delays they latch different data (i.e. latching occurs before the increment filters through).
I have also attached a timing diagram for kuroneko's puzzle. Perhaps you could explain/fix the waitcnt timing implications·to the following jmp. I have "made" it fit the observed results but not sure if it is correct. (note the second part of his puzzle - the add cnt,%xxx ·is incorrect but I just hadn't considered that section properly and·will do this later)
Are the powers to be letting you out of your 'cage' to go to China late January?? *grin*
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Disclaimer: This model explains my observations, but could be completely wrong [noparse]:)[/noparse]
This first came up here http://forums.parallax.com/showthread.php?p=816612
Post Edited (kuroneko) : 12/8/2009 2:47:30 AM GMT