Wow, this is as close to being real as I've heard in a while! I don't know what a "shuttle" is, but I hope I can snag a few...
Just did a quick calculation and it appears that an entire 6-bit photo at 480x272 (my 4.3" touchscreens) would fit in RAM. That would be exeptionally convenient!
Wonder if we could talk Ken into releasing the package pinout so we can start laying out boards for it...
Has the CORDIC system in each cog been discussed somewhere, and if so could someone point me to that thread? I have an reasonable understanding of how cordic works, could this just be a tangent look-up table, or will it actually be a hardware accelerator?
Alsowolfman: Cordic has been discussed IIRC in both the big PropII thread and on one of the webinars (perhaps March 2009 webinar?)
The cog is limited to 512 longs inheritant by design. Chip mentioned possibly adding extra longs for fifos and data storage. Not sure how this will work. The loading from hub was expected to be·4 longs per cycle and also a block load instruction. Hub access was reduced to 1 in 8 clocks instead of 1 in 16 clocks. There was discussion about cog/hub priority but I don't think this went anywhere.
ROM size is only a small area on the chip, so 256KB is not that much area. It may not be filled on the first release. It would be nice to have USB and Ethernet code support in ROM.
The BIG thing to me is the inclusion of 384KB of hub RAM. RAM size takes a lot of chip area (see the Prop 1 die picture - I do not have a link). This has huge potential. LMM, overlaying, etc.
Prop II will be a microcomputer, not a microcontroller
Package speculation:·QFP84, BGAxx,·PLCC84. The PLCC can be socketed for <$2 from Digikey.
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Ahh - Christmas is gonna come late, but I can wait :-)
Anyone else notice the "Multi-threading within cogs" in Ken's post? (Leon?!) If that's available from SPIN I can easily create combined sensor monitoring, can't I?
@Ken: Your list doesn't seem to include mention of inter-chip comm's - has that been dropped?
Thanks Cluso99, it was in the march webinar. So the cordic system is hardware, that is really cool, right now the cordic algorithm that can be found on these forums takes 200 cycles to do an arc-tangent, if i understand it right it looks like the prop II will do the same in under 30, and most of which will be completed on the side. Its also exciting for assembly to not need to use all of the space for software math functions, multiply divide save 7 longs each, and arctan right now takes up over 40. those 3 alone use 10 percent of the available memory.
Post Edited (Alsowolfman) : 11/22/2009 4:36:52 AM GMT
microcontrolled said...
@Clusso99: No kidding. The biggest thing for me is the large RAM size. The way it's advanced, it could run Windows 98!!!!
@microcontrolled: Oh no,·the blue screen of death·headed for the prop·
@simonl: Multithreading was discussed on the long Prop II thread. It was expected ·· Inter-chip comms: The counters are so much more advanced, I would be surprised if there is not·a way included.
SPIN
Have you all realised this is going to be more than·8 times faster just because of pasm execution. Add to that faster hub access = less waiting to·fetch/store hub data.·Then add the Spin Interpreter·optimisation that I did to gain around 20% (which of course is multiplied by 8+). So, I would expect to see a 10x improvement.
PASM
8 x faster. Plus 16 x faster overlaying if required (2x clock, 2x hub access, 4x longs per access). LMM will be at least 8x faster plus faster hub access = maybe 10x faster.
And we haven't considered overclocking this beast yet
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What we plan to do soon is fabricate a test chip so that we can prove all the subsystems that will go into the final chip. We are still a ways from being done with complete design.
Sorry to let you all down. I'm sure Ken didn't mean that the chip would be for sale in a couple of months when he mentioned a "shuttle run".
A shuttle run is where·a foundry gathers designs from perhaps 40 different fabless chip companies and mixes them onto the same mask set, then fabricates perhaps 20 wafers. Afterwards, the various ICs·are cut out of the wafers, packaged, and then sent back to the customers. This way, mask costs (about $180k) are shared among customers so that they can affordably try out their designs (well, at a cost of about $40k) and receive at least 20 chips.
We will do a shuttle run for the critical guts first, then another if we need to make changes to the guts, based on testing. After that, we will do a full-chip shuttle run, followed by perhaps another, until everything is perfect.
I don't see how it can be 100% backward compatible.
If the pipelining has been changed "160 MHz Clock = 160 MInstructions " surely that has an effect on the logical outcome of some self modifying codes.
There must be some issues with the Port B pins comming into existence.
There must be some issues with code using non-existent HUB addresses (roll-over) that will now have real RAM there.
And so on.
I'm sure the changes that break things will be documented or very soon discovered and minor enough that most programs will not break or can be fixed easily.
I presume running the same binaries as Prop I was never on the table anyway.
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For me, the past is not over yet.
I believe it was characterized as "most programs will require few to no changes", implying a run through the IDE to build for PROP II.
Thanks Chip. No worries here. Plenty to do on Prop I.
I think how you stuck to your guns on Prop I posting up a solid design that has seen no changes since release is bad ***, and worth waiting for. The wait might be painful, but the trade off is then being able to just apply it, with no worries for a really long time. That's a valuable, and highly differentiated value proposition that Parallax should be proud of.
So after Chips post, it seems the Prop2 is more a year away than one quarter. The positive aspect: No need to stop all the current Prop1 projects and waiting for the new chip!
As I said on the other thread... Thanks Chip. Guess we got carried away. Better to wait for a fully functional chip without bugs
BTW: The Prop I will still have it's own market. The Prop II will be a new market, no doubt with some overlap such as memory hogs and better video plus all the new A&D stuff. A commercial project I am working on·would not use the Prop II even if it was available at the same price due to power consumption and chip size.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
Everyone should remember being a kid waiting for Christmas, the more you think about it the longer it takes, these days I hardly think about it and it comes along scarily quickly. So prop II, what prop II? Don't know what you are talking about [noparse];)[/noparse]
But my god what a nice list of potential features!! [noparse]:)[/noparse]
40K for 20 chips, OUCH. That is an expensive hobby to just try "a little tweek, here and there" I am sure the extra wait will be worth it (he says thru gritted teeth)
Still that is only 33% up on the finished Virtex chips that were being wafted at me.
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Style and grace : Nil point
I spoke with Ken about this at the show and was under no illusion that this first run was only for a handful of silicon.
I'ts easy to get carried away when you want that new shiny toy isn't it!
It's still great news though and we already have planned (myself and Baggers) what were could do with that power
Regards,
Coley
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ PropGFX - The home of the Hybrid Development System and PropGFX Lite
Pretty sure it does. One thing Chip did say for sure was that PASM was not going to change, and that new instructions would be incorporated into the gaps in the current one.
If it were possible to use the the first 512 registers as a pointer (keeping 32 bit!) mov a, b would give a way to have nearly infinite address space. The only problem is, how to squeeze out a condition. Maybe, the replace bit could be used. Now the replace bit allows to evaluate the bits without moving data, but this functionality could be done differently. OK, that would destroy some symmetry, but it would open a world.
Probably LMM code will fill this gap nicely on Prop II.
We've got the REP instruction, that does a loop X times, some form of auto increment, decrement, and more instructions between HUB accesses, and more frequent HUB accesses coming.
Those things will put LMM speed in a nice range, compared to what we have now.
In that model, the COG acts like a CPU with lots of internal registers and "microcode" functionality, executing out of HUB memory. I've not done the exercise of estimating what the instruction per second speed will be, but I'm guessing that will be in the neighborhood of what PASM is right now. If so, that's going to be damn sweet.
Comments
Just did a quick calculation and it appears that an entire 6-bit photo at 480x272 (my 4.3" touchscreens) would fit in RAM. That would be exeptionally convenient!
Wonder if we could talk Ken into releasing the package pinout so we can start laying out boards for it...
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My Prop Info&Apps: ·http://www.rayslogic.com/propeller/propeller.htm
Alsowolfman: Cordic has been discussed IIRC in both the big PropII thread and on one of the webinars (perhaps March 2009 webinar?)
The cog is limited to 512 longs inheritant by design. Chip mentioned possibly adding extra longs for fifos and data storage. Not sure how this will work. The loading from hub was expected to be·4 longs per cycle and also a block load instruction. Hub access was reduced to 1 in 8 clocks instead of 1 in 16 clocks. There was discussion about cog/hub priority but I don't think this went anywhere.
ROM size is only a small area on the chip, so 256KB is not that much area. It may not be filled on the first release. It would be nice to have USB and Ethernet code support in ROM.
The BIG thing to me is the inclusion of 384KB of hub RAM. RAM size takes a lot of chip area (see the Prop 1 die picture - I do not have a link). This has huge potential. LMM, overlaying, etc.
Prop II will be a microcomputer, not a microcontroller
Package speculation:·QFP84, BGAxx,·PLCC84. The PLCC can be socketed for <$2 from Digikey.
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
(for those anti-Windows people out there,) but we wouldn't want to ruin it, would we?
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Computers are microcontrolled.
Robots are microcontrolled.
I am microcontrolled.
But you·can·call me micro.
Want to·experiment with the SX or just put together a cool project?
SX Spinning light display·
Want cheap wholesale electronic parts?
Transistor parts wholesale
I'd be ready to duck shoes talking like that! [noparse];)[/noparse]
OBC
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New to the Propeller?
Visit the: The Propeller Pages @ Warranty Void.
Anyone else notice the "Multi-threading within cogs" in Ken's post? (Leon?!) If that's available from SPIN I can easily create combined sensor monitoring, can't I?
@Ken: Your list doesn't seem to include mention of inter-chip comm's - has that been dropped?
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Cheers,
Simon
www.norfolkhelicopterclub.com
Announcement: To cut costs in the current economic climate, we have switched-off the light at the end of the tunnel.
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24 bit LCD Breakout Board coming soon. $21.99 has backlight driver and touch sensitive decoder.
Post Edited (Alsowolfman) : 11/22/2009 4:36:52 AM GMT
This is good news. Any idea when we will know what the SPIN/PASM language changes will be?
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Catalina - a FREE C compiler for the Propeller - see Catalina
@simonl: Multithreading was discussed on the long Prop II thread. It was expected
SPIN
Have you all realised this is going to be more than·8 times faster just because of pasm execution. Add to that faster hub access = less waiting to·fetch/store hub data.·Then add the Spin Interpreter·optimisation that I did to gain around 20% (which of course is multiplied by 8+). So, I would expect to see a 10x improvement.
PASM
8 x faster. Plus 16 x faster overlaying if required (2x clock, 2x hub access, 4x longs per access). LMM will be at least 8x faster plus faster hub access = maybe 10x faster.
And we haven't considered overclocking this beast yet
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
What we plan to do soon is fabricate a test chip so that we can prove all the subsystems that will go into the final chip. We are still a ways from being done with complete design.
Sorry to let you all down. I'm sure Ken didn't mean that the chip would be for sale in a couple of months when he mentioned a "shuttle run".
A shuttle run is where·a foundry gathers designs from perhaps 40 different fabless chip companies and mixes them onto the same mask set, then fabricates perhaps 20 wafers. Afterwards, the various ICs·are cut out of the wafers, packaged, and then sent back to the customers. This way, mask costs (about $180k) are shared among customers so that they can affordably try out their designs (well, at a cost of about $40k) and receive at least 20 chips.
We will do a shuttle run for the critical guts first, then another if we need to make changes to the guts, based on testing. After that, we will do a full-chip shuttle run, followed by perhaps another, until everything is perfect.
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Chip Gracey
Parallax, Inc.
If the pipelining has been changed "160 MHz Clock = 160 MInstructions " surely that has an effect on the logical outcome of some self modifying codes.
There must be some issues with the Port B pins comming into existence.
There must be some issues with code using non-existent HUB addresses (roll-over) that will now have real RAM there.
And so on.
I'm sure the changes that break things will be documented or very soon discovered and minor enough that most programs will not break or can be fixed easily.
I presume running the same binaries as Prop I was never on the table anyway.
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For me, the past is not over yet.
Post Edited (heater) : 11/22/2009 8:43:54 AM GMT
I believe it was characterized as "most programs will require few to no changes", implying a run through the IDE to build for PROP II.
Thanks Chip. No worries here. Plenty to do on Prop I.
I think how you stuck to your guns on Prop I posting up a solid design that has seen no changes since release is bad ***, and worth waiting for. The wait might be painful, but the trade off is then being able to just apply it, with no worries for a really long time. That's a valuable, and highly differentiated value proposition that Parallax should be proud of.
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Propeller Wiki: Share the coolness!
Chat in real time with other Propellerheads on IRC #propeller @ freenode.net
Safety Tip: Life is as good as YOU think it is!
I think you mean this one: http://forums.parallax.com/showthread.php?p=746473
It has a lot of information about possible features and changes.
So after Chips post, it seems the Prop2 is more a year away than one quarter. The positive aspect: No need to stop all the current Prop1 projects and waiting for the new chip!
Andy
BTW: The Prop I will still have it's own market. The Prop II will be a new market, no doubt with some overlap such as memory hogs and better video plus all the new A&D stuff. A commercial project I am working on·would not use the Prop II even if it was available at the same price due to power consumption and chip size.
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Post Edited (Cluso99) : 11/22/2009 10:01:08 AM GMT
But my god what a nice list of potential features!! [noparse]:)[/noparse]
But Baggers, we need that demo!!
Graham
Still that is only 33% up on the finished Virtex chips that were being wafted at me.
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Style and grace : Nil point
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
I'ts easy to get carried away when you want that new shiny toy isn't it!
It's still great news though and we already have planned (myself and Baggers) what were could do with that power
Regards,
Coley
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PropGFX - The home of the Hybrid Development System and PropGFX Lite
I paid the equivalent of $2k a chip for T800 transputer samples 24 years ago!
Leon
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Amateur radio callsign: G1HSM
Was that the chip Atari was working on? I remember something about Atari and a transputer.
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Jim Fouch
FOUCH SOFTWARE
Well, one thing is clear. Prop II will have enough power to totally serve as a Prop I & II dev station.
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Propeller Wiki: Share the coolness!
Chat in real time with other Propellerheads on IRC #propeller @ freenode.net
Safety Tip: Life is as good as YOU think it is!
It used a Mega ST for i/o iirc.
www.classiccmp.org/dunfield/atw800/index.htm
Regards,
Coley
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PropGFX - The home of the Hybrid Development System and PropGFX Lite
BAD, KEN!! BAD!! *raps Ken's knuckles with a ruler*
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Propeller Wiki: Share the coolness!
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Count the number of op-codes with all variants and you'll see that there is no place left for even a single additional address bit.
Nick
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Never use force, just go for a bigger hammer!
The DIY Digital-Readout for mills, lathes etc.:
YADRO
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24 bit LCD Breakout Board coming soon. $21.99 has backlight driver and touch sensitive decoder.
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cmapspublic3.ihmc.us:80/servlet/SBReadResourceServlet?rid=1181572927203_421963583_5511&partName=htmltext
Hello Rest Of The World
Hello Debris
Install a propeller and blow them away
We've got the REP instruction, that does a loop X times, some form of auto increment, decrement, and more instructions between HUB accesses, and more frequent HUB accesses coming.
Those things will put LMM speed in a nice range, compared to what we have now.
In that model, the COG acts like a CPU with lots of internal registers and "microcode" functionality, executing out of HUB memory. I've not done the exercise of estimating what the instruction per second speed will be, but I'm guessing that will be in the neighborhood of what PASM is right now. If so, that's going to be damn sweet.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Propeller Wiki: Share the coolness!
Chat in real time with other Propellerheads on IRC #propeller @ freenode.net
Safety Tip: Life is as good as YOU think it is!