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what pins best to use? — Parallax Forums

what pins best to use?

mctriviamctrivia Posts: 3,772
edited 2009-11-30 00:31 in Propeller 1
4 address lines, 3 address latch
8 data lines
re#
we#
cs

what pins would you recomend for fastest access to the 128MB RAM?

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Comments

  • MagIO2MagIO2 Posts: 2,243
    edited 2009-11-11 19:23
    PortPin 0 - 7 for data lines
    PortPin 9 - 15 for the adress + latch
    This way you can use the movs and movd instructions for fast setting. Otherwise you have to do masking to avoid changing the control signals.

    PortPin 8 and PortPin 17 should be unused if controlled by the same COG, so you don't need to take care of the MSB when writing 8 bit with a 9 bit instruction.

    For the control signals you can use whatever pins you want starting from PortPin 18.
  • Dr_AculaDr_Acula Posts: 5,484
    edited 2009-11-12 01:56
    Can you post some more info? I'm playing round with memory chips at the moment, both in spin and pasm. Using P0-7 as data, and a few more pins for latching etc. Still working on the optimum solution.

    Q: 128Mb? or Kb?. If Mb, what sort of chip/module is that?
    And something I've realised - you don't need /CS on a ram chip. Just leave it selected all the time and use /RD and /WR. Saves a pin...

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 02:29
    128MB I have 54 modules of my own making coming in a week. They are 8MWord/16MByte modules that can be stacked up to 8 high. Morphius will be the best place to use these but I have started designing a board for the Propeller System Module to use these modules also and was wondering what pins to use.


    See RAM RAM RAM for more about my modules.

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    Post Edited (mctrivia) : 11/12/2009 2:35:13 AM GMT
  • Dr_AculaDr_Acula Posts: 5,484
    edited 2009-11-12 02:50
    PSRAM, right? Do you have a part number/rough idea of a schematic? In a general sense, there are all sorts of combinations of pins, but if you start at P0 and work up, less pins=slower and more pins=faster. A 3 pin serial ram would be the slowest. I'm using a 12 pin solution which has the best (or worst) of both worlds. Cluso went for a full 28 pin solution. It is a very hard question to answer. How many pins have you got spare?

    As for which pins, I'm not 100% sure it matters. If you use P0-7 and send out a data 1 byte at a time, you still need to mask the high (>7) bits out, then or them with the address mask. And if you put address from P0 up and data further up, it is the other way round but (I think) the same number of ops. Sooner or later, something needs a shift, and I think a shift 1 bit is the same speed as a shift 20 bits, so that doesn't really matter either. For a ballpark figure, I got code writing a single byte to a static ram over 12 lines in 25 instructions. I think Cluso did it in 16, but that included some out-of-bounds checking as well, so maybe it could be 12 or 13 instructions. It probably is easiest to start with P0-7 as a data bus.

    The instructions tend to take the form of - get a long, shift it, AND mask it, OR it with something else, output it by toggling something. 6 instructions, but sometimes 5 if there is no shifting. So I don't think it matters which pins you use.

    16megabytes would very nice though... 128megabytes would be scary!

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    Post Edited (Dr_Acula) : 11/12/2009 3:05:07 AM GMT
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 03:07
    Well the modules will be for sale soon. Will post my schematic tomorrow after I manage to route. The movd movs alignment should give nice speed bost especially with my modules burst mode.

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  • VIRANDVIRAND Posts: 656
    edited 2009-11-12 07:42
    It is possible and has been done on many MicroProcessors to use the data bus to load the address latches first and then access the RAM. Examples intel 8085 and 8031, although in these examples only one address byte is latched prior to data and the other has its own pins.

    I don't know if what I imagine actually exists but it would be really nice if the low address bits could be loaded into a latch which is capable of counting up ... and down too, why not? If you do CPLD or FPGA programs, a versatile latch could really speed up your access time as long as the code to drive it is fast, tight, and transparent (for example two PUBs, RDRAM() and WRRAM(), or if it isn't too anachronistic, POKE and PEEK). You probably could command the latch very fast with longs through a COG Video Generator I think.

    Sometimes I lose a few bytes of data in my SRAMs when everything else is powered down, and I never completely solved that problem, but I sure wish that the /WR pin was active high instead of active low, as that is an obvious possible cause of data loss.
  • Dr_AculaDr_Acula Posts: 5,484
    edited 2009-11-12 09:00
    Virand, good suggestions and that is exactly what Cluso has done for the triblade (and which I've copied, but all credit to him!). A latch can run as fast as PASM can run on a 5Mhz xtal, ie you set up the lines, then toggle a line low then high. No delay needed. I've also run signals through a 138 and this introduces a slight delay so one NOP is needed. But it is still very fast. As far as latches that count, maybe you could use an old-school programmable counter (though these only do nibbles I think so you would need two). But it may be no faster than PASM with an increment then toggling a line.

    I'm looking forward to mctrivia's schematic - in particular how the memory chip actually addresses 16mb. Is it just a lot of pins? And if so, since memory is usually addressed in blocks, maybe you can set the higher addresses and change them less frequently? Burst mode sounds intriguing too.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 12:44
    No need for programmable counter with this module. in burst mode you set first address and just keep toggling clock pin.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 14:36
    Here is the schematic I am working with so far. As you can see i have scrambled the Data bits to the RAM. I did this to allow for better routing. Since they are read and writen in the same order every time though it will not effect the functionality. The only thing I have not finished is routing power and the control lines.

    I have not made a 3D model of the memory modules yet so on the simulation you just need to imagine 25.8mm long pins sticking out of the board. My modules can be soldered on up to 8 high.

    Yes 128MB is a lot of RAM I would like to see someone try to use it all up with a prop.

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  • David BDavid B Posts: 592
    edited 2009-11-12 16:39
    "Yes 128MB is a lot of RAM I would like to see someone try to use it all up with a prop."

    Don't forget what Bill Gates supposedly said about the PC "640K ought to be enough for anybody"

    It sure would be great to have something like a wiki page with a table outlining all the RAM variations available - type, cost, byte capacity, pin requirements, burst access speed, random access speed, read speed vs. write speed, power requirements, etc.

    There are just so many variations of RAM -

    cog RAM - maybe the fastest, cheap, but limited in size
    hub RAM - still pretty fast, also cheap with a little more size
    static RAM with multiplexed addressing - expensive but relatively fast and fairly large capacity, needs lots of pins
    static RAM with external counter addressing - maybe the fastest large capacity solution; fewer pins needed
    dynamic RAM - much less expensize, fairly large capacity, need lots of pins, often free as surplus
    SDRAM - like DRAM but self-refreshes, relatively expensive
    SD card(s) - very few pins needed
    serial EEPROM - relatively small, slow
    FRAM - reads wear them out
    CMOS clock RAM - extremely low power for a few bytes of nonvolatile storage
    hard disk - probably currently the highest capacity, relatively slow, often free as surplus; needs lots of pins, needs lots of power

    And maybe another wiki section with tips and tricks for the best pin access - using the movi, movd, movs commands, using cog counters to generate addresses and/or RAS/CAS/WE pulses, etc.
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 16:45
    Well my modules are
    70ns random
    20ns near(different a3-0)
    7ns burst(133mhz)

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  • David BDavid B Posts: 592
    edited 2009-11-12 18:21
    Those are fast access numbers for the module by itself, but what speeds can be practically achieved when using actual code to access the full range of the RAM?

    I'm in sort of the same boat as Dr_Acula - I've been working with a 30 pin SIMM on a prof development board, just basically getting experience trying to work out optimum pins and commands for different ways to do addressing if the goal is to access a megabyte or more pretty fast.

    30 pin SIMMs also multiplex adresses, so the addressing problem is similar to the SDRAM board - it's not too hard to get really fast access to a small block of the RAM if you fix the higher address lines, but if you want to read or write every location, the instructions to manage the extra bits really start to add up.

    Maybe a mix of propeller addressing the high address lines, with the SDRAM burst writing to the lower addresses might get good results?
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 18:27
    Burst can be really quick.

    Set start address
    clk*3
    Read
    Clk
    Read
    Clk
    Read...

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  • David BDavid B Posts: 592
    edited 2009-11-12 19:04
    The SDRAM datasheet says it can burst up to a page. I'm not sure how large a page is, maybe up to 4K?

    But what if you're trying to digitize music or data or something and you want several megabytes of samples recorded at equal time intervals. How much processing has to be done to set up the next burst write?

    I'm not trying to disparage burst mode; I'm just trying to look at an actual application of SDRAM to see how it would perform over the entire capacity of storage.
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 19:07
    I am using psram and it can burst 8m at a time. In byte mode it is split into 2 pages

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-12 23:23
    D0-D7 tied to P0-P7
    A0-A3 tied to P9-P12
    L0-L2 tied to P13-P15
    Re# tied to P18
    Wr# tied to P19
    CS tied to P20

    have not roted yet but
    CLK tied to P21
    ADV# tied to P22

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    Post Edited (mctrivia) : 11/13/2009 4:46:50 AM GMT
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  • Dr_AculaDr_Acula Posts: 5,484
    edited 2009-11-13 04:39
    That looks a very nifty circuit. How much are those chips (what is the part #) and are they available from different suppliers?

    Going off on a slight tangent, David B please keep us all posted with the SIMM developments.

    On the schematic, where do /WR etc go? (there are 6 pins in a group at the right). Do these go to other prop pins or to another latch or something else?

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-13 04:49
    in my last post i listed what pins i am attached them to. clk and adv are only needed for burst mode.

    Cre got grounded as there is no way with this schematic to effectively work with the registers and they really only effect low power modes.

    the ics are only about 50c each. you can read the part number on the sim though obviously you need to use the 3.3v versions.

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  • Dr_AculaDr_Acula Posts: 5,484
    edited 2009-11-13 05:04
    Ah, sorry, missed that. Ok, so pins 0-22. Still leaves quite a few free for serial, TV out etc. With the price I can see the attractiveness of all this.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-13 06:02
    i suspect gadget gangster will be making these adapters available soon. i have no control over what price he will be asking though.

    It can be wired on perf board but a pcb kit would be much better.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-11-13 22:58
    i just want to correct my earlier statement. burst mode can only do up to 128bytes at a time. I completely mis read the data sheet.

    Also CS is important. With these modules you can only hold CS high for 4uS max.

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  • David BDavid B Posts: 592
    edited 2009-11-14 00:10
    That's what I thought I'd read! The data sheets go into all this fixed vs. variable latency with their restrictions, and fixed vs. continuous burst mode with their restrictions, and I thought you'd found some mode variation I wasn't able to figure out.

    Thanks for the update.
  • Mike HuseltonMike Huselton Posts: 746
    edited 2009-11-14 01:19
    See the following for an intro to PSRAM: download.micron.com/pdf/technotes/CellularRAM/tn4530_psram_101.pdf

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  • jazzedjazzed Posts: 11,803
    edited 2009-11-28 20:35
    So, what is the status of this project? If nothing else, a breakout board with a 1.8V regulator option and all pins would be very useful.

    The biggest PSRAM I see on digikey is 128Mbits and 16bit wide data (8bit are not generally available?). The WAIT pin also needs to be connected for 7ns operation. For asynchronous SRAM-like operation, the 20ns access time is limiting for higher speed bursts, but eliminating the need to use extra pins can be useful especially given the possibilities for Propeller I (near 8MB) and II (<2GB) direct access. There should be more attention given to a PSRAM solution. PSRAM cost per MB at 20ns -vs- 10ns SRAM is appealing at ~ $10/8MB -vs- $10/1MB ... only 16bit PSRAM devices appear to be generally available for higher density. The power cost is much less ... orders of magnitude.

    So, what's up?
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-28 20:44
    I have designed 2 breakout boards for my module. Both contain the needed voltage regulator and some kind of latch/CPLD to reduce the pin count needed. I am not producing the modules and have not been given permission to say what there status is though I will ask.

    What I can say is I have received all the parts to build 25 of my RAM Modules and I will finally be receiving the PCB on Monday.

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  • jazzedjazzed Posts: 11,803
    edited 2009-11-28 21:18
    OK[noparse]:)[/noparse]
    Where did you find a part with 26 address lines. I guess I was looking at the wrong spec. I like your "bank select" method via byte lane enable.
  • mctriviamctrivia Posts: 3,772
    edited 2009-11-28 21:31
    3 address lines are for module select.

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  • Bill HenningBill Henning Posts: 6,445
    edited 2009-11-29 17:26
    Matthew was kind enough not to spill the beans yet - but he asked me if I would smile.gif

    He designed a nice adapter module for Morpheus, however due to production time, testing time, etc., the Morpheus adapter won't be on the market until sometime in January.

    I will make an "official" announcement after I have the boards and tested them - at which time I will order a production run. I don't yet have exact pricing for the adapter board, however I am trying to make it as affordable as possibe - which is why I went "off-shore" for manufacturing.
    jazzed said...
    So, what is the status of this project? If nothing else, a breakout board with a 1.8V regulator option and all pins would be very useful.

    The biggest PSRAM I see on digikey is 128Mbits and 16bit wide data (8bit are not generally available?). The WAIT pin also needs to be connected for 7ns operation. For asynchronous SRAM-like operation, the 20ns access time is limiting for higher speed bursts, but eliminating the need to use extra pins can be useful especially given the possibilities for Propeller I (near 8MB) and II (<2GB) direct access. There should be more attention given to a PSRAM solution. PSRAM cost per MB at 20ns -vs- 10ns SRAM is appealing at ~ $10/8MB -vs- $10/1MB ... only 16bit PSRAM devices appear to be generally available for higher density. The power cost is much less ... orders of magnitude.

    So, what's up?
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  • Nick McClickNick McClick Posts: 1,003
    edited 2009-11-29 21:35
    Hey Jazzed!

    I got the Propeller Platform expansion PCB's in-house late last week - I'm sending a few over to mctrivia to validate his design. Once the design is validated, I'll make them available as a project. If everything checks out, they should be available in about 2 weeks.

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  • jazzedjazzed Posts: 11,803
    edited 2009-11-29 21:51
    So, there are 8 16MB modules on one board? I would be happy with just one 16MB module [noparse]:)[/noparse]
    I hope that WAIT signal is connected for synchronous mode .... Good luck guys.
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