@heater: Absolutely true. It's like those isometric drawings, where an object will "pop out", or "poke in" depending on your mental perspective at the time. COGs are like that for sure.
Frankly, I just see them as having their own memory space now. What to call it is up in the air. It just is. What you do with that memory space, is kind of up to the need really.
Edit: After thinking about it, this is another challenge, similar to the one heater and I just wrote on. The instructions are all the same size, execute in the same time (minus hub ops), and there are not that many of them. However, the bit fields permit a lot of different results, which kind of boils down to CISC.
IMHO, this is a matter of perception.
The actual design is challenging, because it is unique.
Looking at the CDC6600 and comparing it to the Prop, the most glaring difference is that the Prop has no CPU! — just peripheral interface controllers* (i.e. data channels, but which all share the same I/O). Its hub controller is akin to the '6600's stunt box, but that's it: no master control unit.
-Phil
*"Peripheral Interface Controller" is where the Microchip (n
The prop is a multi-processor on a chip. IMHO, this is different than having multiple cores on chip. There are actually 8 CPU's, and they operate concurrently, and do not impact each other, unless the programmer explicitly codes for that.
The HUB is just a manifestation of the minimal logic required for shared resources according to a single rule.
IMHO, the differentiator happens to be the COG having it's own non-associative to the shared HUB memory, addressing space that is distinctly different from the shared memory. That's where the concurrent multi-processing element comes from.
Edit: After thinking about it, this is another challenge, similar to the one heater and I just wrote on. The instructions are all the same size, execute in the same time (minus hub ops), and there are not that many of them. However, the bit fields permit a lot of different results, which kind of boils down to CISC.
IMHO, this is a matter of perception.
The actual design is challenging, because it is unique.
Well, I see an awful lot of that in the Propeller, but for cycle time. Really though, that's arbitrary, and that definition is in the context of A CPU operating with RAM.
The prop is different enough to not be boxed like that. It's my opinion more RISC elements exist than not, and given the highly differentiated design, RISC is then is warranted as a general statement as to the experience, or feel, one would have programming the Prop.
When I see CISC, I so often relate that to distinct instructions, registers, workflows, etc... all aimed at specific tasks. There are remarkably few of those on the prop, and where they exist, they are for the dedicated, on chip, functions. If we are to be talking design, I think those are out of scope as a MCU is quite a different beast than a more general purpose, larger scale CPU.
About half way down, there is CISC and RISC in red and blue. IMHO, more of the RISC attributes appear in the Propeller design than not. I would lean RISC.
It's a lot like MIPS, but for the propeller using an implicit destination, source mode, instead of two operands and a stated destination. The efficiencies of this basically allows a COG to use the memory the way it does. Any atomic element of memory is either instruction or data, or both. That's pretty cool, and somewhat unique as well.
Most other processors I've worked with don't have that particular attribute. The primary unit of memory is smaller than an instruction. COG's don't address on a byte level. Memory just is numbered, and that's it. Simple, and challenging to the definitions above, IMHO. An address is just an address, be it an instruction or data.
Because of this, I think I take back the dilemma noted earlier. IMHO, RISC is more applicable to the Propeller than CISC is. Never mind the number of instruction permutations. I don't think that's relevant, as it's only a small sub-set of what is CISC.
I think that's the heart of the RISC concept!· Use small opcodes so you fit instruction+data into 32 bits and then use a smaller set of instructions that run fast...
I think it's also very worth noting the simple, atomic memory addressing in a COG, eliminates a lot of complexity where dealing with more granular memory and instruction pipes is concerned. That part of the design I find particularly elegant. There's nothing else today really like it.
I think that's the heart of the RISC concept! Use small opcodes so you fit instruction+data into 32 bits and then use a smaller set of instructions that run fast...
RISC isn't a single concept; it also requires a load and store architecture, pipelining, a small instruction set and single-clock instructions.
"RISC" isn't mentioned anywhere in the Propeller Manual, BTW.
Leon
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RISC doesn't require a small instruction set. That's a misconception... It just requires reducing the instructions to those that run fast and fit into·instruction size...
If all look precissely on one COG .... IT is not CPU ... It most like one MICRO with its own RAM and REG's. No mather that all RAM can be USED as REG's else most of it as RAM storage.
That give Propeler not competitor in it's own class.
With other Words ..... Propeller is ........ 8 Micros in same package with shared I/O
and Shared Memory storage unit.
Regards
Christoffer J
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Rayman said...
RISC doesn't require a small instruction set. That's a misconception... It just requires reducing the instructions to those that run fast and fit into instruction size...
It's definitely RISC.
But what about pipelining and single-clock instructions? They are required for a RISC device. XMOS has them, BTW, and is also closer to RISC in that operations like ADD have three register operands, and the original data are not overwritten.
Leon
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I think "single clock" is arbitrary. Single, with respect to what? Some designs internalize smaller clocks to get stuff done, others externalize this, where multiple clocks are seen. The key here is that each instruction occupies a discrete unit of time. That's the primary differentiator between a RISC and CISC design, where instructions / time are concerned. CISC chips have short instructions, and very long ones. This is done to optimize the overall throughput for tasks, and code size. If I were to cite anything in favor of the prop being more RISC, it's that the COG does not do either of those things. There are instructions, they take a unit of time, and they are all the same size, operating consistently.
The few instructions that violate this are linked to dedicated function units, and that's just an artifact common to differences between theory and real world implementation. For the purposes of core discussion on uniqueness and design attributes, this has to be acceptable, or no meaningful discussion can occur.
The implementation in the Propeller is remarkable, as I noted before, for the simplicity of the pipeline, because of how the instructions and memory addressing were done. I do not believe the combination of these things exists anywhere else as implemented in the Propeller. IMHO, a simple pipe is both efficient and consistent. This is one element that contributes to the deterministic behavior seen in most Propeller code. It is a primary element, combined with the rule based shared memory access, where obtaining deterministic behavior is concerned. I will also submit at this time, realizing deterministic behavior is considerably easier on Propeller than other designs, particularly where multi-processing, or just multiple processes needing to occur is concerned. That's the magic right there folks!
So then, we arrive at some sort of impasse!
Either we force a rather unique chip into a box (not realistic)
,or
we make generalized observations (done on this thread in an attempt to discuss the design --IMHO perfectly reasonable)
,or
we invoke new characterizations that then can be defined and applied to the discussion as a whole.
I would add, I feel considerably challenged by the idea of "multi-core" -vs- "concurrent multi-processing". These two overlap to me, and I have trouble differentiating them.
I'd class it as a unique architecture, it definitely isn't RISC in the commonly accepted meaning of the term, or CISC. The designers have never classified it as RISC, as I said earlier.
Leon
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Well, I think that would be an excellent webinar (god I hate that word) topic. Design influences and motivations leading up to the Propeller. We've got material on the latter, but we don't have all that much on the former.
And, we have a standing disagreement, in that the weighting you have assigned to relevant elements of what is RISC are simply different than mine are. No worries. I feel pretty good about RISC like, and so there it is.
Since we have established uniqueness, EISC then?
[noparse]:)[/noparse]
(yeah, I'm in for a bit of sport this morning here)
potatohead said...
I would add, I feel considerably challenged by the idea of "multi-core" -vs- "concurrent multi-processing". These two overlap to me, and I have trouble differentiating them.
MIMD and SIMD are more meaningful.
Leon
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Well, that's in the context of super computing, and does speak to multi-core -vs- multi-processing. Fair enough, but also a different level of comparison / characterization, no?
A MIMD design, can be implemented CISC or RISC like, yes?
Yeah, after a bit of consideration, those are apt.
So then, considering the entire Propeller, not just a COG, MIMD for sure, but again, not quite! The data path to the HUB is sequential, not multiple. Another blending of ideas seen in the prop [noparse]:)[/noparse]
Getting back to the pipeline and single-clock instructions: the Propeller has both.
But, frankly, the RISC vs. CISC argument is just plain silly, not unlike counting angels dancing on the head of a pin. Who cares? It is what it is and doesn't need categorizing to use it. I'd rather spend my time programming the Prop than debating over which pigeon hole it belongs in.
Comments
Frankly, I just see them as having their own memory space now. What to call it is up in the air. It just is. What you do with that memory space, is kind of up to the need really.
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(nobody saw it, your status is fine, trust me [noparse]:)[/noparse]
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Edit: After thinking about it, this is another challenge, similar to the one heater and I just wrote on. The instructions are all the same size, execute in the same time (minus hub ops), and there are not that many of them. However, the bit fields permit a lot of different results, which kind of boils down to CISC.
IMHO, this is a matter of perception.
The actual design is challenging, because it is unique.
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Post Edited (potatohead) : 10/17/2009 4:42:25 PM GMT
-Phil
*"Peripheral Interface Controller" is where the Microchip (n
The prop is a multi-processor on a chip. IMHO, this is different than having multiple cores on chip. There are actually 8 CPU's, and they operate concurrently, and do not impact each other, unless the programmer explicitly codes for that.
The HUB is just a manifestation of the minimal logic required for shared resources according to a single rule.
IMHO, the differentiator happens to be the COG having it's own non-associative to the shared HUB memory, addressing space that is distinctly different from the shared memory. That's where the concurrent multi-processing element comes from.
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Post Edited (potatohead) : 10/17/2009 4:47:25 PM GMT
cse.stanford.edu/class/sophomore-college/projects-00/risc/whatis/index.html
They ought to know.
Leon
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The prop is different enough to not be boxed like that. It's my opinion more RISC elements exist than not, and given the highly differentiated design, RISC is then is warranted as a general statement as to the experience, or feel, one would have programming the Prop.
When I see CISC, I so often relate that to distinct instructions, registers, workflows, etc... all aimed at specific tasks. There are remarkably few of those on the prop, and where they exist, they are for the dedicated, on chip, functions. If we are to be talking design, I think those are out of scope as a MCU is quite a different beast than a more general purpose, larger scale CPU.
Edit: I think this paper, from the same site, illustrates the dilemma perfectly: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/risccisc/index.html
About half way down, there is CISC and RISC in red and blue. IMHO, more of the RISC attributes appear in the Propeller design than not. I would lean RISC.
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Post Edited (potatohead) : 10/17/2009 4:54:31 PM GMT
Most other processors I've worked with don't have that particular attribute. The primary unit of memory is smaller than an instruction. COG's don't address on a byte level. Memory just is numbered, and that's it. Simple, and challenging to the definitions above, IMHO. An address is just an address, be it an instruction or data.
Because of this, I think I take back the dilemma noted earlier. IMHO, RISC is more applicable to the Propeller than CISC is. Never mind the number of instruction permutations. I don't think that's relevant, as it's only a small sub-set of what is CISC.
Sorry.
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RISC isn't a single concept; it also requires a load and store architecture, pipelining, a small instruction set and single-clock instructions.
"RISC" isn't mentioned anywhere in the Propeller Manual, BTW.
Leon
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Post Edited (Leon) : 10/17/2009 5:15:01 PM GMT
Do we need to say "RISC Like" ? [noparse]:)[/noparse]
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It's definitely RISC.
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Post Edited (Rayman) : 10/17/2009 5:23:12 PM GMT
"Elegant Instruction Set Count" = high, on Propeller. There, done. Unique, right? LOL!!
IMHO, this thread illustrates perfectly the uniqueness of the chip. QED.
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I both agre and NOT with YOUrs.
If all look precissely on one COG .... IT is not CPU ... It most like one MICRO with its own RAM and REG's. No mather that all RAM can be USED as REG's else most of it as RAM storage.
That give Propeler not competitor in it's own class.
With other Words ..... Propeller is ........ 8 Micros in same package with shared I/O
and Shared Memory storage unit.
Regards
Christoffer J
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha
But what about pipelining and single-clock instructions? They are required for a RISC device. XMOS has them, BTW, and is also closer to RISC in that operations like ADD have three register operands, and the original data are not overwritten.
Leon
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Post Edited (Leon) : 10/17/2009 5:44:38 PM GMT
The few instructions that violate this are linked to dedicated function units, and that's just an artifact common to differences between theory and real world implementation. For the purposes of core discussion on uniqueness and design attributes, this has to be acceptable, or no meaningful discussion can occur.
The implementation in the Propeller is remarkable, as I noted before, for the simplicity of the pipeline, because of how the instructions and memory addressing were done. I do not believe the combination of these things exists anywhere else as implemented in the Propeller. IMHO, a simple pipe is both efficient and consistent. This is one element that contributes to the deterministic behavior seen in most Propeller code. It is a primary element, combined with the rule based shared memory access, where obtaining deterministic behavior is concerned. I will also submit at this time, realizing deterministic behavior is considerably easier on Propeller than other designs, particularly where multi-processing, or just multiple processes needing to occur is concerned. That's the magic right there folks!
So then, we arrive at some sort of impasse!
Either we force a rather unique chip into a box (not realistic)
,or
we make generalized observations (done on this thread in an attempt to discuss the design --IMHO perfectly reasonable)
,or
we invoke new characterizations that then can be defined and applied to the discussion as a whole.
Which then?
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Post Edited (potatohead) : 10/17/2009 5:44:03 PM GMT
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Leon
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And, we have a standing disagreement, in that the weighting you have assigned to relevant elements of what is RISC are simply different than mine are. No worries. I feel pretty good about RISC like, and so there it is.
Since we have established uniqueness, EISC then?
[noparse]:)[/noparse]
(yeah, I'm in for a bit of sport this morning here)
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MIMD and SIMD are more meaningful.
Leon
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A MIMD design, can be implemented CISC or RISC like, yes?
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So then, considering the entire Propeller, not just a COG, MIMD for sure, but again, not quite! The data path to the HUB is sequential, not multiple. Another blending of ideas seen in the prop [noparse]:)[/noparse]
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But, frankly, the RISC vs. CISC argument is just plain silly, not unlike counting angels dancing on the head of a pin. Who cares? It is what it is and doesn't need categorizing to use it. I'd rather spend my time programming the Prop than debating over which pigeon hole it belongs in.
-Phil
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