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CPLD based VGA and memory controller. Respinned ! - Page 2 — Parallax Forums

CPLD based VGA and memory controller. Respinned !

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  • heaterheater Posts: 3,370
    edited 2009-10-03 16:36
    Ale: Why is it not what you want ?

    Looks to me what you and many others want here is:
    1) Something to ease adding external RAM to the Prop
    2) Something to help with VGA

    So surely any old "black box" that does that is what you want, whether it be CPLD, FPGA, a pile of TTL or some processor based solution. Who cares what's inside as long it works. Choose the best solution based on the usual criteria: cost, size, power consumption, easy of implementation, etc etc. Or am I missing something here?

    "but having a propeller in the mix brings... nothing." Here I have to disagree somewhat. The Prop and the XMOS are very different beasts. The Prop and Spin and Pasm and the Propeller Tool are uniquely simple system to explore and implement embedded systems. The XMOS does not come anywhere close. Yes it may have "more this" and "faster that" but I don't see it as a Prop replacement unless one is willing to climb a steep hill of learning, C, XC, the mapper, the tool chain etc etc. Many people would rather just quickly get a job done or actually have fun doing it [noparse]:)[/noparse]

    No, I'm just suggesting it's used as that tiny black box that just helps the Prop along it's way and the internals of which no normal Prop user would ever have to worry about.

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  • potatoheadpotatohead Posts: 10,261
    edited 2009-10-03 16:54
    What is needed on VGA, btw. Is it just RAM?

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  • AleAle Posts: 2,363
    edited 2009-10-03 18:08
    heater: With the amount of experience I have with the XMOS, the propeller does not bring anything. And well, I do not use Spin and I do not have any problems with C, XC or the XMOS tools. The only advantage is: I have 4 spare propeller chips on my desk and only 1 XMOS chip that is soldered to a board. I just wanted to give a project I have in mind some... front end, to put it simple, and I thought it could be a nice (and not too difficult) project for other people.

    Well, after some more thoughts and coding the controller still does not fit in the CPLD. I'll need a '144 or maybe split it into a 9572 and a 9536. Here is the code, maybe someone can trim it, who knows.

    It does fit in a 95144

    `timescale 1ns / 1ps
    //////////////////////////////////////////////////////////////////////////////////
    // Company: 
    // Engineer: Pacito.Sys hppacito <@> gmail.com
    // 
    // Create Date:    18:04:13 10/03/2009 
    // Design Name: 
    // Module Name:    top 
    // Project Name: 
    // Target Devices: 
    // Tool versions: 
    // Description: A VGA and memory controller for the propeller
    //
    // Dependencies: 
    //
    // Revision: 
    // Revision 0.01 - File Created
    // Additional Comments: 
    //
    //////////////////////////////////////////////////////////////////////////////////
    module top(
        output [noparse][[/noparse]18:0] m_addr, // Memory address
        inout [noparse][[/noparse]7:0] m_data, // memory ddata bus
        output m_nce, // memory chip enable
        output m_noe, // memory output enable
        output m_nwe, // memory write enable
        //output m_nlb,
        //output m_nhb,
        //output vga_vsync,
        //output vga_hsync,
        output [noparse][[/noparse]2:0] vga_r, // VGA red bits
        output [noparse][[/noparse]2:0] vga_g, // VGA green bits
        output [noparse][[/noparse]1:0] vga_b, // VGA blue bits
        input in_clk, // input clock, two times desired pixel clock
        input in_pixel_en, // clock enable, pixel clock will be active when this signal is 1
        //input in_vsync,
        //input in_hsync,
        input in_cmdw, // commad write signal
        input in_dataw, // data write signal
        input in_datar, // data read signal
        inout [noparse][[/noparse]7:0] in_data // data bus to propeller
        );
         
    parameter MEM_AWIDTH = 19;
    parameter MEM_DWIDTH = 8;
    parameter MAX_PIXELS = 307200;
    reg [noparse][[/noparse]MEM_AWIDTH-1:0] r_pixel_counter;
    reg [noparse][[/noparse]MEM_AWIDTH-1:0] r_memory_ptr;
    //reg [noparse][[/noparse]MEM_AWIDTH-1:0] r_max_pixel; // replaced by a constant
    reg [noparse][[/noparse]7:0] r_vga_out;
    reg clk_pixel;
    reg clk_mem;
    //reg r_memread;
    //reg r_memwrite;
    reg [noparse][[/noparse]1:0] r_ridx;
    reg [noparse][[/noparse]7:0] r_tindata;
    reg [noparse][[/noparse]7:0] r_toutdata;
    
    initial begin
        r_vga_out = 0;
        clk_pixel = 1;
        clk_mem = 0;
    end
    // VGA handling
    //assign vga_vsync = in_vsync;
    //assign vga_hsync = in_hsync;
    assign vga_r = r_vga_out[noparse][[/noparse]2:0];
    assign vga_g = r_vga_out[noparse][[/noparse]5:3];
    assign vga_b = r_vga_out[noparse][[/noparse]7:6];
    
    // Propeller <-> CPLD comm
    
    // every other clock we refresh the display if needed
    always @ (posedge in_clk) begin
        clk_pixel = ~clk_pixel;
        clk_mem = ~clk_mem;
    end
    // Command write on the rising edge
    always @ (posedge in_cmdw)
        r_ridx [noparse][[/noparse]1:0] = in_data[noparse][[/noparse]1:0];
        
    // Value write to the right register on the falling edge
    always @ (negedge in_cmdw)
    begin
       case (r_ridx[noparse][[/noparse]1:0])
            2'b00: r_memory_ptr[noparse][[/noparse]7:0] = in_data;
            2'b01: r_memory_ptr[noparse][[/noparse]15:8] = in_data;
            2'b10: r_memory_ptr[noparse][[/noparse]MEM_AWIDTH-1:16] = in_data[noparse][[/noparse]MEM_AWIDTH-17:0];
            2'b11: r_memory_ptr[noparse][[/noparse]MEM_AWIDTH-1:16] = in_data[noparse][[/noparse]MEM_AWIDTH-17:0]; // we do the same...
        endcase
    end
    
    // Memory control
    assign m_nce = ((clk_pixel & in_pixel_en) | (clk_mem & (in_datar | in_dataw))) ? 0:1;
    assign m_noe = ((clk_pixel & in_pixel_en) | (clk_mem & in_datar)) ? 0:1;
    assign m_nwe = ((clk_pixel & in_pixel_en) | (clk_mem & in_dataw)) ? 0:1;
    // VGA Refresh
    always @ (negedge clk_pixel)
        r_vga_out = m_data; // loads memory data
        
    always @ (negedge clk_mem)
    begin
        if (in_datar == 1) begin
            r_toutdata = m_data;
        end
    end
    
    // Writes to memory, saves to external latch
    always @ (posedge clk_mem)
    begin
        if (in_dataw == 1) begin r_tindata = in_data; end
    end
    
    // Increments pointer
    always @ (posedge clk_pixel) 
    begin
        if (in_pixel_en == 1) begin
            r_pixel_counter = r_pixel_counter + 1;
        end
        if (r_pixel_counter == MAX_PIXELS) begin
            r_pixel_counter = 0;
        end
    end
    // CPLD<->Propeller interface
    assign in_data = (in_datar == 1) ? r_toutdata:8'bz;
    assign m_data = (in_dataw == 1) ? r_tindata:8'bz;
    assign m_addr = (clk_pixel & in_pixel_en) ? r_pixel_counter:r_memory_ptr;
    
    endmodule
    
    
    

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  • BTXBTX Posts: 674
    edited 2009-10-03 19:18
    Ale.
    I dont' see close your code but, why you don't clock the propeller data into the CPLD using one pchip pin and then do:

    always @ (pchip_pin)
    begin
     //Catch the pchip data here and store in SRAM
     //inc SRAM address 
    end
    

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    Regards.

    Alberto.
  • AleAle Posts: 2,363
    edited 2009-10-03 19:48
    That can be done, but it will still do not fit :-(. Incrementing for reads and writes will be added. thanks Alberto.

    That small code needs ~5% of a XC3S50

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  • BradCBradC Posts: 2,601
    edited 2009-10-04 03:05
    mctrivia said...
    i use a stencil on my prop modules to solder the qfn chips and all parts on the top. the botom half i do by hand. i could use a stencil but i would have to build a rig to hold it flat.

    I thought you might. I was wondering about the practicalities for a home assembler when you offered to sell blank boards.

    How do you apply the paste manually? I see there are quite a few automated syringe units out there for repeatability. Do you do it by hand?

    BGA is starting to sound more interesting, but doing double layered boards at home is not quite at the density required to do BGA. At least QFN/LQFP and so on is workable for the home hacker.

    I guess I'm still stuck in the previous decade, where 4 layer boards required a second mortgage on a kidney just for the setup fees.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-10-04 03:44
    4 layer are not that expensive.

    For 155 sq inches electrical testing 4/4 trace width clearance and gold plating I will be paying $480

    I use stencil because it is faster to assemble multiple boards. Syringes do work and before I found a place that would make cheap stencils I used them.

    This board should be nice being al bga. I could make 2 layer but emi would be really bad.

    I think the xmos would be the way to go if it did not mater what pins I used. If pin order mattered then pcb design would take many more layers or be much bigger.

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  • AleAle Posts: 2,363
    edited 2009-10-04 15:48
    So, now I'm going for a FPGA design: It's 10x5 cm. I'll get several of these boards so some maybe available. Please, do not complain about the use of a DIP Propeller: It can be used for other projects when needed!

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  • AleAle Posts: 2,363
    edited 2009-10-05 15:08
    In the mean time, i.e. while I decide whit what I'm going to fill the rest of that board shown above, I come to the following layout with a XC95144XL. Those CPLDs cost some 6.6 Euro and are available in TQFP100 among other packages.The good is that it is still a single side board if I can get it done somewhere. The code fits! so I hope it also works, time to simulate!

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  • SapiehaSapieha Posts: 2,964
    edited 2009-10-05 15:15
    Hi Ale.

    If posible draw +power line with Propeller XTal that you have around both XTal pins GND lines.
    It give You more stable frequency on Propeller

    Regards
    Christoffer J

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  • AleAle Posts: 2,363
    edited 2009-10-14 09:55
    Well, I redesigned this board using two CPLDs (because I have them and I can't do myself, for the time being, a board for 0.5mm fine pitch parts) and updated the two first posts accordingly.

    Notes:

    A Wiki at propeller.wikispaces.org/Propeller_CPLD has been created for this page. I'll add all details and files there. For the time being the page is orphaned. I'll add it to the project list when it is more or less complete.

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  • SapiehaSapieha Posts: 2,964
    edited 2009-10-14 13:44
    Hi Ale.

    Nice Board.
    One posiblity - istead of solder XTal direct - use 2 machine pins (same as in 40pin connector) and You can change XTal without ned of resolder it.

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    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


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  • AleAle Posts: 2,363
    edited 2009-10-14 13:46
    Yes I'll do that if I redo this board. thanks. Now I'm more concerned with getting it to work, at any frequency wink.gif

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  • SapiehaSapieha Posts: 2,964
    edited 2009-10-14 13:56
    Hi Ale.

    If I can see correct You have some short on solder (XTal) at last

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    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


    Sapieha
  • AleAle Posts: 2,363
    edited 2009-10-14 14:45
    Yes, there was a short on the xtal and on the small CPLD. Boards with solder mask are friendlier :-D

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  • Bill HenningBill Henning Posts: 6,445
    edited 2009-10-14 16:53
    Nice work!
    Ale said...
    Well, I redesigned this board using two CPLDs (because I have them and I can't do myself, for the time being, a board for 0.5mm fine pitch parts) and updated the two first posts accordingly.

    Notes:

    A Wiki at propeller.wikispaces.org/Propeller_CPLD has been created for this page. I'll add all details and files there. For the time being the page is orphaned. I'll add it to the project list when it is more or less complete.
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  • AleAle Posts: 2,363
    edited 2009-10-26 08:30
    Well,

    after fighting my way with Verilog I made it work. At least I can read and write the memory at arbitrary positions. Reading requires a dummy instruction between asserting the read signal that I use to negate it:

    c6_readdata             call    #c6_writeaddr
    
                            or      OUTA, c6_cnt_datar
                            andn    OUTA, c6_cnt_datar
                            mov     c6_v_data0, INA
                            mov     c6_v_data1, INA
                            mov     c6_v_data2, INA
                            mov     c6_v_data3, INA
    c6_readdata_ret         ret
    
    



    For testing 4 reads are issued to see where the data ends, I mean due to pipeline in the design... but with a 50 MHz clock the data show in the first read of INA:

    Test, new run..._
    55555555
    Test, new run...
    55555555
    Test, new run...
    66666666
    Test, new run...
    77777777
    Test, new run...
    77777777
    Test, new run...
    77777777
    Test, new run...
    77777777
    
    



    The test code is shown in the wiki.

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