@hinv - yes, I mistakenly said HUB instead of COG, thank you for pointing out that semantic. The fact remains you have 512 longs or 2KB of COG RAM and you can only execute instructions from COG RAM. I'm sorry to be a bit trollish but your argument seems a bit ad hominem as it still does not address my original argument that no matter how much DRAM you slap on it you are still limited to 2KB of COG RAM to execute machine code. Unless the SPIN code has a one to one relationship with machine code and the interpreter can execute SPIN instructions in the same time that they would execute in native machine code then you are still limiting yourself greatly by sticking with SPIN. This is why most time critical code is written in spin assembly which is translated directly to machine code. If you just want more room for high level applications, a 2GB SDRAM card will suffice for that. You can swap all the SPIN code you want from that. The folks at parallax could even make the SPIN interpreter smarter with branch prefetching and caching. I still don't see the buy off you get for the complexity of adding DRAM.
@potatohead - exactly, the LMM (or whatever you want to call the SPIN extender) will be the only thing that benefits from adding DRAM. As Mike Green pointed out already, this is targeting a niche market. Not everyone wants or needs to use LMM, nor do they want the complexity and added cost for what is required to support LMM.
@awesomeduck - sorry about the confusion. Take a look at the datasheet and it explains it all. All machine instructions are executed from COG RAM which is 512 32bit cells or 2KB. The 32KB of HUB RAM is where SPIN byte code is stored and read from by the SPIN interpreter. The SPIN interpreter runs in COG RAM and is machine code.
ImageCraft said...
So help me out here, for a non-hardware guy like me. Lets say we have the 64 IO pin Prop B, what fast can it interface with external SRAM? Because if such beast exist, and the external memory interface is fast enough, that would pretty much make a "Prop C chip" a reality.
Depending on we manage the memory map and what the memory driver instructions look like, it may even be possible that the user can put "fast" code in HUB RAM, and other code in external SRAM. Or a RTOS can sit in the HUB RAM (see http://www.imagecraft.com/pub/emos_avr.pdf for our eMOS RTOS), and the user tasks can sit in the external SRAM. Or...
Imagine the possibilities! Most people are not bumping up to the limit of processing power with the Prop 1 yet, it's mostly the memory limitation that is the wall. So Prop 1 B could solve that. When Prop II comes out, that will address the processing limits end of thing.
So what's the theoretical throughput of external SRAM?
The answer to your question is very fast. Using a single cog to interface with the SRAM it would take 2 instructions per memory read, 1 to set the new address, 1 to read the data or 10 milliion per second. If you used 2 cogs, 1 to to set the address another to read the data 3 clock cycles after the address is set you could achieve 20 million per second. Neither of these examples takes into account any·looping or incrementing instructions. Writing can achieve the same speeds if you set it up properly, that is the /OE is high during the duration. The first instruction sets the address,·data·and sets·the /WE·low, the second instruction sets the /WE high. You can use two cogs to achieve double the throughput. Switching between read and writing takes an extra instruction to change the state of /OE.
The Prop 2 could achieve much closer to the limit of the chip (100 million accesses per second).
ImageCraft said...
Most people are not bumping up to the limit of processing power with the Prop 1 yet
It's hard to quantify how true or not that is but there are cases where speed and processing power are issues though I don't know how that impacts generally - I'd perhaps venture most people are happy with what they have or live within the limitations, most 'complaints' being visions of how the Propeller could be even better.
I'll agree memory size is a limitation; for high-res video, for people implementing emulators and VM's, and probably other cases.
I/O size I do not think is so much of an issue except for when it comes to connecting external memory or when external I/O extenders aren't seen as desirable.
Raw processing speed in itself isn't a problem per se in most cases, but it is a psychological problem, especially for LMM and emulators. Even the best 4:1 PASM:LMM speed ratio feels like losing a lot. Going for more complicated LMM, say thumb-style code, and the extra processing required really plunges overall performance. Things like USB are right at the limit of the Prop's capabilities, MP3 decoding beyond it, high-res displays need multiple Cogs and complex interleaving.
I, and I perceive it of others posting here, tend to have their own favourite applications in mind so I'm not sure how such perspectives reflect wider opinion. I think it's certainly true that those people perceive that if the Prop had more Ram, more Cogs, more speed, more this and that their applications would become better, more feasible and more widely useful.
I think the Prop I, IB, II debate is clouded by the 'how do I make my favoured project perfect' question. Limitations are known, solutions can be seen, ideas on next generation are thus forthcoming ( no complaint about that ), but I think the 'I cannot have Prop II so I'll take IB as a stop-gap' is skewing the bigger debate ( though there are other arguments in favour of a IIB, price being the main one IMO ).
I also think Chips' "how about this for the Prop II?" postings also unintentionally skews the debate, giving the impression that there's still a long way to go for the II, it's all up in the air, and, with no timescale promised, people are wanting something now, so the Prop IB, held up only by verification issues and $80K, looks like something to push for in the shorter-term. People always want now or soon, not later.
As an electronics hobbyist, the IB and II will take me way outside my comfort zone of DIY strip-boards; what I'd like to see as a software engineer with limited hardware capabilities is a Prop II with all the whizz-bang processing capabilities it will have in a DIP package and I'd be prepared to lose the extra 32 I/O. A DIP Prop II module will solve that issue if pricing is right.
As much as I'm excited by the Prop II, I have to admit that is tempered by can I use it, can I afford it, is it cost effective, does using it make sense ? Until we get closer to a launch date it's hard to answer.
Yup, everyone has their application requirements. More memory appears to be a most common need.
Having the prop-1b would be nice for larger embedded programs ... embedded linux would be great, but that would still not be doable for various reasons. Other serious things could be enabled with prop-1b though.
@Paul - Even with prop-1b having IO-B dedicated to long data and IO-A controlling address and write enable, 10MB/S read access in one cog is unlikely unless long read is the only thing the cog would do. 10MB/S write in one cog seems impossible. In any event bandwidth would be reduced because of interface requirements. Such a design would still leave a desire for more pins as only 32 - serial - eeprom - write enable - n address bits would be left over.
So really the only big improvement would come from prop-II. But prop-II is something we don't have, can only imagine having, and is really more of a tease or passion stroker than anything; I may never see it in my lifetime. In other words it is practically a pipe dream. Even with prop-II the number of IO pins would limit its usefulness as a general computing solution. At least the bigger internal hub memory and performance enhancements make it much more attractive.
... what I'd like to see as a software engineer with limited hardware capabilities is a Prop II with all the whizz-bang processing capabilities it will have in a DIP package and I'd be prepared to lose the extra 32 I/O.
Thats exactly what I think all the time when I read this thread!
The big big advantage of the existing Propeller is it's 40 Pin Dip and 0.8mm spacing TQFP package. If I go to higher pin count packages, then there are a ton of other controllers, processors, FPGAs which beat the Prop in many aspects.
I definitly wote for a Prop II in 40 Pin DIP option, with only PortA bonded out (and BOEn pin for the 1.x V supply voltage).
But no Prop 1 with 64 port pins (spare the 80k$ to make the PropII-40Pin [noparse]:)[/noparse]
I still have Basic Stamps that I play with, and plan on using SX chips for some time. What Parallax offer the user is a true long term commitment to each product. They do not
seem to offer a "new latest toy" for a quick buck. Because of this, provided the P8x64 is not rediculously expenseive then it clearly will get used over the next few years.
We are all aware that the Prop 2 will be more power hungry and cost more, so even once Prop 2 is out the Prop 1(s) will still have a usefull role to play.
The current economic situation works for and against, at the moment I'm hoping Parallax could get some good deals on fabrication, this may help keep the cost down, so
that when things pick up the P1's are good on the low cost / low power products and the P2 is there for applications which have no constraints.
Chip, would it be possible to package the P8x64 in a similar way for to that planned for Prop 2? (or at least mostly, the 1.8v obviosly not used in P1 designs), if so, this would
enable many of the chaps to start developing applications in an upgradable way.
Yes, I will buy some if available. How many will depend on how succesful my products are.
There are QFP80 with 0.8 mm of pin spacing and the not really popular PLCC84. They said they would not go for the PLCC package and the other one is not really used much either :-(. Well maybe they will put it in a carrier board with PINs even if the user has to solder them, then it could even be BGA !
A SMT or even a BGA package for the PropII or B isn't a show stopper for hobbyists IMO. All Parallax needs to is put it on a carrier circuit board like the way Futurlec does on their ET-SMT32 Stamp. Just plug it in and you're ready to go.
And if it pushes the price to $40-50.00 its still no more expensive than a BS-2 for hobbyists.
I definitly wote for a Prop II in 40 Pin DIP option, with only PortA bonded out (and BOEn pin for the 1.x V supply voltage).
And leave port B un-bonded but useful for IPC (Inter-Process Communication)
Not that I use the Propeller in 40 pin DIP anyway, but I do like the idea..
To be honest the Proto-board has been such a winner for me that I've not used any other form-factor. I have over 10 proto-boards here in various projects [noparse]:)[/noparse]
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Cardinal Fang! Fetch the comfy chair.
i would rather see the full 64io in bga. Adapter boards to dip could easily be made with crystal and caps on adapter board for nose reduction. BGA is a great format for anyone wanting to make small products. Also BGA is extremely easy to solder on as all you have to do if the board has vias under each pin is place it and heat it up with a heat gun. Easier then other surface mount chips.
just a thought. but if you make the prop 2 and prop 1B in BGA only. with same pin outs(obviously leaving some unused in prop1B) then you could make a bga to dip or bga to surface adapters like I said above. If you also included surface mount voltage regulators, surface mount eeprom, and prop plug on the adapters then the addapters could be used as the development board with no periferals attached. main boards could be made for this then that included periferals or adapters to spins studio plugs. If you layed out the board right though it could be made to plug directly into a protoboard making it a very cost effective development tool.
The Problem with the carrier boards is:
If Parallax mount a chip on a little PCB, the cost explodes. (factor 5..10 related to the component costs).
They simply have to protect their Basic Stamp products....
To be fair: all the carrier boards of other chip manufactors are also much more expensive then the chip itself.
So a carrier board will not be the solution, if the chip costs are critical. At the end you have to buy the 80 or 100 pin TQFP with 0.5mmm pitch and sold it yourself.
Sure, if you only work with ProtoBoards, or if you produce a product in high quantities, then this is not relevant. But most Propeller products which I know are in little series or custom made.
I haven't been around embedded prototyping for all that long and after couple of attempts soldering 0.5mm pitch LQFP 48/64 had so far been a breeze for me, even with no magnifying glass whatsoever. I haven't tried 80 or 100 pin packages but figure it's not much harder.
There are plenty of video tutorials on how to do it with reasonably good iron and a soldering wick. The hardest part is to initially align the part's legs with pads
as i said though bga is not hard to solder if you can get access to a heat gun. sure the adapter board would cost about $3 to make and a little more to populate. parallax does not even need to do the populating them selves if they do not have the equipment for mass runs. just make the gerber files or boards available to anyone and others here could make and populate. there is no reason it could not be done for $10+parts and still make a profit.
One thing to consider is that there's a cost to the manufacturer for each package style in which a chip is offered. Adding a DIP package, for example, doesn't come free. Moreover, the more SKUs that are offered, the more capital it takes to maintain an inventory. Considering the low intrinsic sales volume expected from hobbyists, compared to OEM sales, tooling up to produce a reduced-pincount DIP may make little economic sense — especially when a carrier board for for an SMT package would provide the same convenience to the end-user.
As hobbyists and do-it-yourselfers, we all want an IC package that's easy to work with. But we can't produce the million-unit sales for Parallax that justify the expenditure required to provide it. I think Parallax has bent over backward for hobbyists by providinig the Prop I in a 40-pin DIP. But I also think that adding 32 or more pins makes an equally hobbyist-friendly IC package a bit much to expect.
In Parallax's shoes, I would be looking at a fine-pitch quad flatpack that's compact, produces high yields with automated SMT assembly, and doesn't require xrays to inspect. This will likely rule out both the QFN and BGA packages due to yield and inspection issues and PLCCs due to size issues. This pretty much leaves a 0.5mm-pitch PQFP. But even that is not insurmountable for hand assembly.
Good points Phil
Why not just make the 64 IO chip in the smallest(or cheapest) package possible, and provide a Prop2Stamp similar to the PropStamp http://www.parallax.com/Store/Microcontrollers/PropellerTools/tabid/143/CategoryID/19/List/0/SortField/0/catpageindex/2/Level/a/ProductID/448/Default.aspx
for hobbyists? The Prop2Stamp could have 32IOs in a 40pin DIP stamp form factor and if you need all 64 IOs you have to buy the raw chip or a proto/carrier card with the Prop already soldered on. It would also be great if the carrier board had pads for the SRAM and DRAM that ends up being best suited too. [noparse]:)[/noparse]
I don't think the actual package form is a major problem as long as its bonded out on a module
for the people who cannot easily work with those forms but then cost does become an issue. I
appreciate this isn't a problem for the experts or the commercial users but I feel it would be a
great shame for Parallax to lose out on the more amateur market.
Going off at a slight tangent, another issue when the Prop II arrives is what support there will be
for the Prop I when the 'bleeding edge experimenters' move towards that. When the Prop II is
the de-facto platform ( "forget the Prop I, it doesn't have enough speed, ram nor support the
right PASM instructions needed for this" ) will it become the neglected child ( although
I'm sure Parallax will continue to support it ).
hippy said...
When the Prop II is the de-facto platform [noparse][[/noparse]the Prop I] will it become the neglected child...
I seriously don't see this happening at all. The Prop I will have no less horsepower than it does now and, for reasons of price, current consumption, relative complexity, package size, available objects, etc., will continue to be a better fit for many apps than the Prop II. Besides, we've just begun to explore and exploit all that the Prop I is capable of, and this should continue well into the Prop II's ascendency and beyond.
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 2/1/2009 2:41:32 AM GMT
i agree. just because something is faster does not make it better. The prop 1 will still do great for most battery powered devices and things that do not need the extra processing power. 160MIPS can do a fair bit when it comes to imbeded applications. What you will see is everyone working on graphical and vision projects moving to prop 2 because it will have the power and extra ram to make those projects easier.
This is true. Just because P2 exists will not make the great Mike Green (or any of the other Guru's) forget all he knows about P1, and the real strength of these guys is that they answer everybodies questions, no matter how trivial they may seem to the experienced. So P1 support is probably secure. If Parallax do launch a P1b then this will be supported in the same way. In any case P2 (from what Chip has said) is not a different planet, sure there will be more instructions and some advanced techniques for multi-thinging, but it's still a Propellor.
My main hope is that Parallax do what has been suggested above; go for a single package format for both 1a and 2, as you've all said, we don't really care what package, we will cope with what we get. Probably between us producing "breakout" boards and if between us we can support Parallax in this the breakout boards will become cost effective fairly quickly because the non-greed spirit here is clear to see.
The "need for speed" got us all excited, and I agree for the Video developers this is crucial, but in reality, for most "real time microcontroller" apps, P1 is fast enough. The "need for vast memory space" seems to be the new thing (We ask a lot of Chip, don't we?), Cluso and co are making good headway on this. The real limit is the 512 Cog RAM, Chip is obviously aware of this as I have seen discussion of a switched 128 byte extension, but this is more complex for the novice.
(Chip Gracey can ignore the next part, just thinking out aloud )
I've been thinking, that even at this stage, it would be worth Chip investigating a 40-bit architecture, thus turning the 512 limit into 8k, this is probably too much this late on, but it seems to me we are all hoping to see the massively fast P2, but if it spends most of it's time fetching and carrying memory about, it will not be as fast in the application as it says on the pack. Oh it is hard, such a wonderful little processor, so many possibilities for the future (and now), ah well, back to trying to figure....
well at least the hub instructions will be 1 to 8 instead of 7 to 22 cycles to run. If you are going to expand the arcitecture lets keep to a logical number say 48 or 64. 64 bit micro now that would be impresive. though you double your space per instruction.
I will offer right now if no one else is willing i can do a run of 500 boards for $15 each +parts. I can provide pcbs and will solder them all together. I don't care what package it comes as long as it is small. space is at a premium in most of my designs. This would be a small board to addapt to dip that included prop plug, eeprom, crystal, and voltage regulators. you just need to add periferals.
mctrivia said...
Also BGA is extremely easy to solder on as all you have to do if the board has vias under each pin is place it and heat it up with a heat gun. Easier than other surface mount chips.
How do you apply solder tiny paste to each BGA pad before mounting the BGA chip?
That is the hard part.
PQFP is probably best. small and though it scares people can be soldered without any special tools(other then a good iron and fine solder I use 63/37 .015) BGA does require a heat gun.
Comments
@potatohead - exactly, the LMM (or whatever you want to call the SPIN extender) will be the only thing that benefits from adding DRAM. As Mike Green pointed out already, this is targeting a niche market. Not everyone wants or needs to use LMM, nor do they want the complexity and added cost for what is required to support LMM.
@awesomeduck - sorry about the confusion. Take a look at the datasheet and it explains it all. All machine instructions are executed from COG RAM which is 512 32bit cells or 2KB. The 32KB of HUB RAM is where SPIN byte code is stored and read from by the SPIN interpreter. The SPIN interpreter runs in COG RAM and is machine code.
Post Edited (soshimo) : 1/31/2009 8:52:24 AM GMT
The Prop 2 could achieve much closer to the limit of the chip (100 million accesses per second).
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Paul Baker
Post Edited (Paul Baker) : 1/31/2009 9:31:50 AM GMT
It's hard to quantify how true or not that is but there are cases where speed and processing power are issues though I don't know how that impacts generally - I'd perhaps venture most people are happy with what they have or live within the limitations, most 'complaints' being visions of how the Propeller could be even better.
I'll agree memory size is a limitation; for high-res video, for people implementing emulators and VM's, and probably other cases.
I/O size I do not think is so much of an issue except for when it comes to connecting external memory or when external I/O extenders aren't seen as desirable.
Raw processing speed in itself isn't a problem per se in most cases, but it is a psychological problem, especially for LMM and emulators. Even the best 4:1 PASM:LMM speed ratio feels like losing a lot. Going for more complicated LMM, say thumb-style code, and the extra processing required really plunges overall performance. Things like USB are right at the limit of the Prop's capabilities, MP3 decoding beyond it, high-res displays need multiple Cogs and complex interleaving.
I, and I perceive it of others posting here, tend to have their own favourite applications in mind so I'm not sure how such perspectives reflect wider opinion. I think it's certainly true that those people perceive that if the Prop had more Ram, more Cogs, more speed, more this and that their applications would become better, more feasible and more widely useful.
I think the Prop I, IB, II debate is clouded by the 'how do I make my favoured project perfect' question. Limitations are known, solutions can be seen, ideas on next generation are thus forthcoming ( no complaint about that ), but I think the 'I cannot have Prop II so I'll take IB as a stop-gap' is skewing the bigger debate ( though there are other arguments in favour of a IIB, price being the main one IMO ).
I also think Chips' "how about this for the Prop II?" postings also unintentionally skews the debate, giving the impression that there's still a long way to go for the II, it's all up in the air, and, with no timescale promised, people are wanting something now, so the Prop IB, held up only by verification issues and $80K, looks like something to push for in the shorter-term. People always want now or soon, not later.
As an electronics hobbyist, the IB and II will take me way outside my comfort zone of DIY strip-boards; what I'd like to see as a software engineer with limited hardware capabilities is a Prop II with all the whizz-bang processing capabilities it will have in a DIP package and I'd be prepared to lose the extra 32 I/O. A DIP Prop II module will solve that issue if pricing is right.
As much as I'm excited by the Prop II, I have to admit that is tempered by can I use it, can I afford it, is it cost effective, does using it make sense ? Until we get closer to a launch date it's hard to answer.
Having the prop-1b would be nice for larger embedded programs ... embedded linux would be great, but that would still not be doable for various reasons. Other serious things could be enabled with prop-1b though.
@Paul - Even with prop-1b having IO-B dedicated to long data and IO-A controlling address and write enable, 10MB/S read access in one cog is unlikely unless long read is the only thing the cog would do. 10MB/S write in one cog seems impossible. In any event bandwidth would be reduced because of interface requirements. Such a design would still leave a desire for more pins as only 32 - serial - eeprom - write enable - n address bits would be left over.
So really the only big improvement would come from prop-II. But prop-II is something we don't have, can only imagine having, and is really more of a tease or passion stroker than anything; I may never see it in my lifetime. In other words it is practically a pipe dream. Even with prop-II the number of IO pins would limit its usefulness as a general computing solution. At least the bigger internal hub memory and performance enhancements make it much more attractive.
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--Steve
Post Edited (jazzed) : 1/31/2009 3:42:03 PM GMT
Thats exactly what I think all the time when I read this thread!
The big big advantage of the existing Propeller is it's 40 Pin Dip and 0.8mm spacing TQFP package. If I go to higher pin count packages, then there are a ton of other controllers, processors, FPGAs which beat the Prop in many aspects.
I definitly wote for a Prop II in 40 Pin DIP option, with only PortA bonded out (and BOEn pin for the 1.x V supply voltage).
But no Prop 1 with 64 port pins (spare the 80k$ to make the PropII-40Pin [noparse]:)[/noparse]
Andy
seem to offer a "new latest toy" for a quick buck. Because of this, provided the P8x64 is not rediculously expenseive then it clearly will get used over the next few years.
We are all aware that the Prop 2 will be more power hungry and cost more, so even once Prop 2 is out the Prop 1(s) will still have a usefull role to play.
The current economic situation works for and against, at the moment I'm hoping Parallax could get some good deals on fabrication, this may help keep the cost down, so
that when things pick up the P1's are good on the low cost / low power products and the P2 is there for applications which have no constraints.
Chip, would it be possible to package the P8x64 in a similar way for to that planned for Prop 2? (or at least mostly, the 1.8v obviosly not used in P1 designs), if so, this would
enable many of the chaps to start developing applications in an upgradable way.
Yes, I will buy some if available. How many will depend on how succesful my products are.
And if it pushes the price to $40-50.00 its still no more expensive than a BS-2 for hobbyists.
And leave port B un-bonded but useful for IPC (Inter-Process Communication)
Not that I use the Propeller in 40 pin DIP anyway, but I do like the idea..
To be honest the Proto-board has been such a winner for me that I've not used any other form-factor. I have over 10 proto-boards here in various projects [noparse]:)[/noparse]
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Cardinal Fang! Fetch the comfy chair.
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Links to other interesting threads:
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
If Parallax mount a chip on a little PCB, the cost explodes. (factor 5..10 related to the component costs).
They simply have to protect their Basic Stamp products....
To be fair: all the carrier boards of other chip manufactors are also much more expensive then the chip itself.
So a carrier board will not be the solution, if the chip costs are critical. At the end you have to buy the 80 or 100 pin TQFP with 0.5mmm pitch and sold it yourself.
Sure, if you only work with ProtoBoards, or if you produce a product in high quantities, then this is not relevant. But most Propeller products which I know are in little series or custom made.
Andy
There are plenty of video tutorials on how to do it with reasonably good iron and a soldering wick. The hardest part is to initially align the part's legs with pads
As hobbyists and do-it-yourselfers, we all want an IC package that's easy to work with. But we can't produce the million-unit sales for Parallax that justify the expenditure required to provide it. I think Parallax has bent over backward for hobbyists by providinig the Prop I in a 40-pin DIP. But I also think that adding 32 or more pins makes an equally hobbyist-friendly IC package a bit much to expect.
In Parallax's shoes, I would be looking at a fine-pitch quad flatpack that's compact, produces high yields with automated SMT assembly, and doesn't require xrays to inspect. This will likely rule out both the QFN and BGA packages due to yield and inspection issues and PLCCs due to size issues. This pretty much leaves a 0.5mm-pitch PQFP. But even that is not insurmountable for hand assembly.
-Phil
Why not just make the 64 IO chip in the smallest(or cheapest) package possible, and provide a Prop2Stamp similar to the PropStamp http://www.parallax.com/Store/Microcontrollers/PropellerTools/tabid/143/CategoryID/19/List/0/SortField/0/catpageindex/2/Level/a/ProductID/448/Default.aspx
for hobbyists? The Prop2Stamp could have 32IOs in a 40pin DIP stamp form factor and if you need all 64 IOs you have to buy the raw chip or a proto/carrier card with the Prop already soldered on. It would also be great if the carrier board had pads for the SRAM and DRAM that ends up being best suited too. [noparse]:)[/noparse]
for the people who cannot easily work with those forms but then cost does become an issue. I
appreciate this isn't a problem for the experts or the commercial users but I feel it would be a
great shame for Parallax to lose out on the more amateur market.
Going off at a slight tangent, another issue when the Prop II arrives is what support there will be
for the Prop I when the 'bleeding edge experimenters' move towards that. When the Prop II is
the de-facto platform ( "forget the Prop I, it doesn't have enough speed, ram nor support the
right PASM instructions needed for this" ) will it become the neglected child ( although
I'm sure Parallax will continue to support it ).
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 2/1/2009 2:41:32 AM GMT
My main hope is that Parallax do what has been suggested above; go for a single package format for both 1a and 2, as you've all said, we don't really care what package, we will cope with what we get. Probably between us producing "breakout" boards and if between us we can support Parallax in this the breakout boards will become cost effective fairly quickly because the non-greed spirit here is clear to see.
The "need for speed" got us all excited, and I agree for the Video developers this is crucial, but in reality, for most "real time microcontroller" apps, P1 is fast enough. The "need for vast memory space" seems to be the new thing (We ask a lot of Chip, don't we?), Cluso and co are making good headway on this. The real limit is the 512 Cog RAM, Chip is obviously aware of this as I have seen discussion of a switched 128 byte extension, but this is more complex for the novice.
(Chip Gracey can ignore the next part, just thinking out aloud
I've been thinking, that even at this stage, it would be worth Chip investigating a 40-bit architecture, thus turning the 512 limit into 8k, this is probably too much this late on, but it seems to me we are all hoping to see the massively fast P2, but if it spends most of it's time fetching and carrying memory about, it will not be as fast in the application as it says on the pack. Oh it is hard, such a wonderful little processor, so many possibilities for the future (and now), ah well, back to trying to figure....
I will offer right now if no one else is willing i can do a run of 500 boards for $15 each +parts. I can provide pcbs and will solder them all together. I don't care what package it comes as long as it is small. space is at a premium in most of my designs. This would be a small board to addapt to dip that included prop plug, eeprom, crystal, and voltage regulators. you just need to add periferals.
How do you apply solder tiny paste to each BGA pad before mounting the BGA chip?
That is the hard part.
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